DS90CF386MTD National Semiconductor, DS90CF386MTD Datasheet - Page 11
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DS90CF386MTD
Manufacturer Part Number
DS90CF386MTD
Description
Line Receiver IC
Manufacturer
National Semiconductor
Specifications of DS90CF386MTD
Peak Reflow Compatible (260 C)
No
Supply Voltage Max
3.30V
Leaded Process Compatible
No
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DS90CF386MTD
Manufacturer:
NS
Quantity:
47
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Part Number:
DS90CF386MTD
Manufacturer:
national
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Manufacturer:
NS/国半
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Part Number:
DS90CF386MTDX
Manufacturer:
NS/国半
Quantity:
20 000
Part Number:
DS90CF386MTDX NOPB
Manufacturer:
TI/德州仪器
Quantity:
20 000
Company:
Part Number:
DS90CF386MTDX/NOPB
Manufacturer:
TI
Quantity:
3 132
Part Number:
DS90CF386MTDX/NOPB
Manufacturer:
TI/德州仪器
Quantity:
20 000
RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DOWN
V
GND
PLL V
PLL GND
LVDS V
LVDS GND
RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
FPSHIFT OUT
PWR DOWN
V
GND
PLL V
PLL GND
LVDS V
DS90CF386 MTD56 Package Pin Descriptions—24-Bit FPD Link Receiver
DS90CF366 MTD48 Package Pin Descriptions—18-Bit FPD Link Receiver
DS90CF386 — 64 ball FBGA package Pin Descriptions —
FPD Link Receiver
CC
RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DOWN
V
GND
PLL V
PLL GND
LVDS V
LVDS GND
CC
Pin Name
Pin Name
CC
Pin Name
CC
CC
CC
CC
CC
CC
I/O
I/O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I/O
O
O
I
I
I
I
I
I
I
I
I
I
I
No.
No.
21
28
3
3
1
1
1
1
4
5
1
2
1
3
4
4
1
1
1
1
4
5
1
2
1
No.
Positive LVDS differentiaI data inputs.
Negative LVDS differential data inputs.
TTL level data outputs. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines — FPLINE,
FPFRAME, DRDY (also referred to as HSYNC, VSYNC, Data Enable).
Positive LVDS differential clock input.
Negative LVDS differential clock input.
TTL Ievel clock output. The falling edge acts as data strobe.
TTL level input. When asserted (low input) the receiver outputs are low.
Power supply pins for TTL outputs.
Ground pins for TTL outputs.
Power supply for PLL.
Ground pin for PLL.
Power supply pin for LVDS inputs.
Ground pins for LVDS inputs.
Positive LVDS differentiaI data inputs.
Negative LVDS differential data inputs.
TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines — FPLINE,
FPFRAME, DRDY (also referred to as HSYNC, VSYNC, Data Enable).
Positive LVDS differential clock input.
Negative LVDS differential clock input.
TTL Ievel clock output. The falling edge acts as data strobe. Pin name RxCLK OUT.
TTL level input. When asserted (low input) the receiver outputs are low.
Power supply pins for TTL outputs.
Ground pins for TTL outputs.
Power supply for PLL.
Ground pin for PLL.
Power supply pin for LVDS inputs.
28
4
4
1
1
1
1
4
5
1
2
1
3
Positive LVDS differentiaI data inputs.
Negative LVDS differential data inputs.
TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 3 control
lines — FPLINE, FPFRAME, DRDY (also referred to as HSYNC, VSYNC, Data
Enable).
Positive LVDS differential clock input.
Negative LVDS differential clock input.
TTL Ievel clock output. The falling edge acts as data strobe.
TTL level input. When asserted (low input) the receiver outputs are low.
Power supply pins for TTL outputs.
Ground pins for TTL outputs.
Power supply for PLL.
Ground pin for PLL.
Power supply pin for LVDS inputs.
Ground pins for LVDS inputs.
11
Description
Description
Description
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