DS90CR285MTD National Semiconductor, DS90CR285MTD Datasheet - Page 13

• Manufacturer Part Number: DS90CR285MTD
• Description: Transmitter IC
• Manufacturer: National Semiconductor

Specifications of DS90CR285MTD

• Peak Reflow Compatible (260 C): No
• Supply Voltage: 3.3V
• Supply Voltage Max: 3.3V
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

TxIN
TxOUT+
TxOUT−
TxCLK IN
TxCLK OUT+
TxCLK OUT−
PWR DWN
V
GND
PLL V
PLL GND
LVDS V
LVDS GND
RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DWN
V
GND
PLL V
AC Timing Diagrams
C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
Tppos — Transmitter output pulse position (min and max)
RSKM ≥ Cable Skew (type, length) + Source Clock Jitter (cycle to cycle)(Note 11) + ISI (Inter-symbol interference)(Note 12)
Cable Skew — typically 10 ps–40 ps per foot, media dependent
Note 11: Cycle-to-cycle jitter is less than 250 ps
Note 12: ISI is dependent on interconnect length; may be zero
Pin Descriptions
CC
CC
Pin Name
Pin Name
CC
CC
CC
DS90CR285 MTD56 (TSSOP) Package Pin Description — Channel Link Transmitter
I/O
DS90CR286 MTD56 (TSSOP) Package Pin Description — Channel Link Receiver
I/O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
No.
No.
28
28
4
4
1
1
1
1
4
5
1
2
1
3
4
4
1
1
1
1
4
5
1
TTL level input.
Positive LVDS differential data output.
Negative LVDS differential data output.
TTL IeveI clock input. The rising edge acts as data strobe. Pin name TxCLK IN.
Positive LVDS differential clock output.
Negative LVDS differential clock output.
TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power
down.
Power supply pins for TTL inputs.
Ground pins for TTL inputs.
Power supply pin for PLL.
Ground pins for PLL.
Power supply pin for LVDS outputs.
Ground pins for LVDS outputs.
Positive LVDS differential data inputs.
Negative LVDS differential data inputs.
TTL level data outputs.
Positive LVDS differential clock input.
Negative LVDS differential clock input.
TTL level clock output. The rising edge acts as data strobe. Pin name RxCLK OUT.
TTL level input.When asserted (low input) the receiver outputs are low.
Power supply pins for TTL outputs.
Ground pins for TTL outputs.
Power supply for PLL.
(Continued)
FIGURE 18. Receiver LVDS Input Skew Margin
13
Description
Description
01291020
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