DSPIC30F2011T-30I/SO Microchip Technology, DSPIC30F2011T-30I/SO Datasheet - Page 4
![IC,DSP,16-BIT,CMOS,SOP,18PIN,PLASTIC](/photos/6/76/67656/150-18-soic_sml.jpg)
DSPIC30F2011T-30I/SO
Manufacturer Part Number
DSPIC30F2011T-30I/SO
Description
IC,DSP,16-BIT,CMOS,SOP,18PIN,PLASTIC
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20ISO.pdf
(210 pages)
3.DSPIC30F2011-20ISO.pdf
(14 pages)
4.DSPIC30F2011-20ISO.pdf
(6 pages)
5.DSPIC30F2011-20ISO.pdf
(18 pages)
6.DSPIC30F2011-20IP.pdf
(26 pages)
Specifications of DSPIC30F2011T-30I/SO
Rohs Compliant
YES
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
12KB (4K x 24)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
18-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC30F005 - MODULE SCKT DSPIC30F 18DIP/SOIC
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
dsPIC30F Family Reference Manual
Register 35-1:
DS70272B-page 35-4
Upper Byte:
bit 15
bit 15
bit 14
bit 13
bit 12-7
bit 6
bit 5-2
bit 1
bit 0
SPIEN
R/W-0
SPIEN: SPI1 Enable bit
1 = Enables the module and configures SCK1, SDO1, SDI1 and SS1 as serial port pins
0 = Disables the module
Unimplemented: Read as ‘0’
SPISIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
Unimplemented: Read as ‘0’
SPIROV: Receive Overflow Flag bit
1 = A new byte/word was completely received and discarded. The user application has not read the
0 = No overflow has occurred
Unimplemented: Read as ‘0’
SPITBF: SPI1 Transmit Buffer Full Status bit
1 = Transmit has not yet started; SPI1TXB is full
0 = Transmit has started; SPI1TXB is empty
Automatically set in hardware when the CPU writes SPI1BUF location, loading SPI1TXB.
Automatically cleared in hardware when the SPI1 module transfers data from SPI1TXB to SPI1SR.
SPIRBF: SPI1 Receive Buffer Full Status bit
1 = Receive is complete; SPI1RXB is full
0 = Receive is not complete; SPI1RXB is empty
Automatically set in hardware when the SPI1 module transfers data from SPI1SR to SPI1RXB.
Automatically cleared in hardware when the core reads SPI1BUF location, reading SPI1RXB.
Legend:
R = Readable bit
-n = Value at POR
previous data in the SPI1BUF register.
U-0
—
SPI1STAT: SPI1 Status and Control Register
Lower Byte:
bit 7
U-0
—
SPISIDL
R/W-0
SPIROV
R/C-0
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
U-0
—
U-0
—
U-0
—
U-0
—
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
U-0
—
U-0
—
U-0
—
U-0
—
© 2008 Microchip Technology Inc.
U-0
—
x = Bit is unknown
bit 8
SPITBF
R-0
SPIRBF
R-0
bit 0