DSPIC30F2023T-30I/PT Microchip Technology, DSPIC30F2023T-30I/PT Datasheet - Page 133
![12KB, Flash, 512bytes-RAM, 30MIPS, 35I/O, 16-bit Family,nanoWatt 44 TQFP 10x10x1](/photos/6/82/68251/c04-076_pt_sml.jpg)
DSPIC30F2023T-30I/PT
Manufacturer Part Number
DSPIC30F2023T-30I/PT
Description
12KB, Flash, 512bytes-RAM, 30MIPS, 35I/O, 16-bit Family,nanoWatt 44 TQFP 10x10x1
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.AC164335.pdf
(286 pages)
2.DM300023.pdf
(22 pages)
3.DM300023.pdf
(18 pages)
4.DSPIC30F2011-20ISO.pdf
(66 pages)
5.DSPIC30F2011-20IP.pdf
(26 pages)
6.DSPIC30F1010-30ISO.pdf
(26 pages)
7.DSPIC30F1010-30ISO.pdf
(50 pages)
Specifications of DSPIC30F2023T-30I/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
12KB (4K x 24)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F2023T-30I/PTTR
Available stocks
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Quantity
Price
Company:
Part Number:
DSPIC30F2023T-30I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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DSPIC30F2023T-30I/PT
Manufacturer:
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- AC164335 PDF datasheet
- DM300023 PDF datasheet #2
- DM300023 PDF datasheet #3
- DSPIC30F2011-20ISO PDF datasheet #4
- DSPIC30F2011-20IP PDF datasheet #5
- DSPIC30F1010-30ISO PDF datasheet #6
- DSPIC30F1010-30ISO PDF datasheet #7
- Current page: 133 of 286
- Download datasheet (5Mb)
FIGURE 12-19:
12.19 PWM Interrupts
The PWM module can generate interrupts based on
internal timing or based on external signals via the cur-
rent-limit and Fault inputs. The primary time base mod-
ule can generate an interrupt request when a special
event occurs. Each PWM generator module has its
own interrupt request signal to the interrupt controller.
The interrupt for each PWM generator is an OR of the
trigger event interrupt request, the current-limit input
event or the Fault input event for that module.
There are four interrupt request signals to the interrupt
control plus another interrupt request from the primary
time base on special events.
12.20 PWM Time Base Interrupts
The PWM module can generate interrupts based on
the primary time base and/or the individual time bases
in each PWM generator. The interrupt timing is speci-
fied by the Special Event Comparison Register
(SEVTCMP) for the primary time base, and by the
TRIGx registers for the individual time bases in the
PWM generator modules.
The primary time base special event interrupt is
enabled via the SEIEN bit in the PTCON register. The
individual time base interrupts generated by the trigger
logic in each PWM generator are controlled by the
TRGIEN bit in the PWMCONx registers.
© 2006 Microchip Technology Inc.
PWM TRIGGER BLOCK DIAGRAM
TRIGx Write
Clk
15
15
Compare Logic
TRIGx Register
PTMRx
Preliminary
PDI
PDI
=
12.21 PWM Fault and Current-Limit Pins
The PWM module supports multiple Fault pins for each
PWM generator. These pins are labeled SFLTx
(Shared Fault) or IFLTx (Individual Fault). The Shared
Fault pins can be seen and used by any of the PWM
generators. The Individual Fault pins are usable by
specific PWM generators.
Each PWM generator can have one pin for use as a
cycle-by-cycle current limit, and another pin for use as
either a cycle-by-cycle current limit or a latching current
Fault disable function.
12.22 Leading Edge Blanking
Each PWM generator supports “Leading Edge Blank-
ing” of the current-limit and Fault inputs via the
LEB<9:3> bits and the PHR, PHF, PLR, PLF, FLTLE-
BEN and CLLEBEN bits in the LEBCONx registers.
The purpose of leading edge blanking is to mask the
transients that occur on the application printed circuit
board when the power transistors are turned on and off.
The LEB bits support the blanking (ignoring) of the cur-
rent-limit and Fault inputs for a period of 0 to 1024 nsec
in 8.4 nsec increments following any specified rising or
falling edge of the coarse PWMH and PWML signals.
The coarse PWM signal (signal prior to the PWM fine
tuning) has resolution of 8.4 nsec (at 30 MIPS), which
is the same time resolution as the LEB counters.
The PHR, PHF, PLR and PLF bits select which edge of
the PWMH and PLWL signals will start the blanking
timer. If a new selected edge triggers the LEB timer
while the timer is still active from a previously selected
PWM edge, the timer reinitializes and continues
counting.
3
3
dsPIC30F1010/202X
TRGDIV<2:0>
Divider
Pulse
DS70178C-page 131
PWMx Trigger
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