DSPIC30F3013T-20E/ML Microchip Technology, DSPIC30F3013T-20E/ML Datasheet - Page 3

• Manufacturer Part Number: DSPIC30F3013T-20E/ML
• Description: IC,DSP,16-BIT,CMOS,LLCC,44PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3013T-20E/ML

• Rohs Compliant: YES
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 24KB (8K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE 2:
© 2010 Microchip Technology Inc.
Note 1:
OSC2 Pin
OSC2 Pin
Oscillator
Module
32 kHz
Power
Low-
ADC
(LP)
I
I
I
2
2
2
C
C
C
Only those issues indicated in the last column apply to the current silicon revision.
Consumption
Bus Collision
Sleep Mode
Using RC15
Addressing
Addressing
for Digital
Feature
in Sleep
SILICON ISSUE SUMMARY (CONTINUED)
Current
10-bit
10-bit
Mode
FRC
I/O
Number
Item
18.
19.
20.
21.
22.
23.
24.
The 10-bit slave does not set the RBF flag or load the I2CxRCV
register, on address match if the Least Significant bits (LSbs) of
the address are the same as the 7-bit reserved addresses.
When the I
address of 0x102, the I2CxRCV register content for the lower
address byte is 0x01 rather than 0x02.
When the I
generates a glitch on the SDA and SCL pins, causing a false
communication start in a single-master configuration or a bus
collision in a multi-master configuration.
The LP oscillator does not function when the device is placed in
Sleep mode.
When the FRC Clock mode is selected, the OSC2 pin cannot be
used for I/O.
For this revision of silicon, if the pin RC15 is required for digital
input/output, the FPR<4:0> bits in the FOSC Configuration Fuse
register may not be set up for FRC w/PLL 4x/8x/16x modes.
If the ADC module is in an enabled state when the device enters
Sleep Mode, the power-down current (I
exceed the device data sheet specifications.
2
2
C module is configured as a 10-bit slave with an
C module is enabled, the dsPIC
Issue Summary
dsPIC30F3012/3013
PD
) of the device may
®
DSC device
DS80448D-page 3
Revisions
B0
Affected
X
X
X
X
X
X
X
B1
X
X
X
X
(1)