EP9301-IQZ Cirrus Logic Inc, EP9301-IQZ Datasheet - Page 14

32-Bit Microcontroller IC

EP9301-IQZ

Manufacturer Part Number
EP9301-IQZ
Description
32-Bit Microcontroller IC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets

Specifications of EP9301-IQZ

Controller Family/series
(ARM9)
Core Size
32 Bit
A/d Converter
12 Bits
Supply Voltage
3.3V
No. Of I/o Pins
24
Mounting Type
Surface Mount
Operating Temperature Min
-40°C
Package / Case
208-LQFP
Core Processor
ARM9
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
 Details
Other names
598-1250

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9301-IQZ
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
EP9301
Entry Level ARM9 System-on-Chip Processor
Memory Interface
Figure 2
values for the timings of each of the SDRAM modes.
SDRAM Load Mode Register Cycle
14
SDCLK high time
SDCLK low time
SDCLK rise/fall time
Signal delay from SDCLK rising edge time
Signal hold from SDCLK rising edge time
DQMn delay from SDCLK rising edge time
DQMn hold from SDCLK rising edge time
DA valid setup to SDCLK rising edge time
DA valid hold from SDCLK rising edge time
SDWEn
SDCLK
SDCSn
DQMn
RASn
CASn
AD
DA
through
Figure 5
t
clkrf
define the timings associated with all phases of the SDRAM. The following table contains the
Parameter
Figure 2. SDRAM Load Mode Register Cycle Timing Measurement
t
d
Copyright 2010 Cirrus Logic (All Rights Reserved)
OP-Code
t
h
Symbol
t
t
clk_high
clk_low
t
t
t
t
t
DQd
DQh
clkrf
DAs
DAh
t
t
d
h
Min
t
clk_low
1
1
2
3
-
-
-
-
-
(t
(t
HCLK
HCLK
Typ
2
-
-
-
-
-
-
t
clk_high
) / 2
) / 2
Max
4
8
8
-
-
-
-
-
-
DS636F2
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns

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