HCS410/SN Microchip Technology, HCS410/SN Datasheet - Page 13

• Manufacturer Part Number: HCS410/SN
• Description: IC,Remote-Control Transmitter/Encoder,CMOS,SOP,8PIN
• Manufacturer: Microchip Technology
• Series: KEELOQ®r
• Type: Code Hopping Encoder and Transponderr

Specifications of HCS410/SN

• Applications: Access Control Systems
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.4
IFF mode allows the decoder to perform an IFF valida-
tion, to write to the user EEPROM and to read from the
user EEPROM. Each operation consists of the decoder
sending an opcode data and the HCS410 giving a
response.
There are two IFF modes: IFF1 and IFF2. IFF1 allows
only one key IFF, while IFF2 allows two keys to be
used.
It is possible to use the HCS410 as an IFF token with-
out using a magnetic field for coupling. The HCS410
can be directly connected to the data line of the
decoder as shown in Figure 2-3. The HCS410 gets its
power from the data line as it would in normal transpon-
der mode. The communication is identical to the com-
munication used in transponder mode.
FIGURE 2-15: MODULATION FOR IFF COMMUNICATION
FIGURE 2-16: OVERVIEW OF IFF OPERATION
 2001 Microchip Technology Inc.
Note:
IFF Mode
Activate
Activate
Activate
0
1
When IFF2 is enabled, seed transmissions
will not be allowed.
previous
Start or
PPM Decoder Commands
bit
Opcode
Opcode
Opcode
3 T
E
16-bit Data
WRITE
READ
5 T
IFF
32/16-bit Challenge
E
T
E
16-bit Data
T
E
Preliminary
2.4.1
The HCS410 will enter IFF mode if the capacitor/induc-
tor resonant circuit generates a voltage greater than
approximately 1.0 volts on LC0. After the verified appli-
cation of power and elapse of the normal reset period,
the device will start responding by pulsing the DATA
line (LC0/1) with pulses as shown in Figure 2-17. This
action will continue until the pulse train is terminated by
receiving a start signal of duration 2T
before the next expected marker pulse. The device
now enters the IFF mode and expects to receive an
‘Opcode’ and a 0/16/32-bit Data-stream to react on.
The data rate (T
configuration word. See Section 3.0 for additional
details.
2.4.2
As shown in Figure 2-15, a logic 1 and 0 are differenti-
ated by the time between two rising edges. A long
pulse indicates a 1; a short pulse, a 0.
0
1
32/16-bit IFF Response
Opcode
PPM Encoder Response
IFF MODE ACTIVATION
IFF DECODER COMMANDS
T
E
E
) is determined by the TBSL bits in the
2 T
T
OK
E
E
T
E
HCS410
E
DS40158E-page 13
, on the LC inputs
Opcode
Opcode