LM2641MTC-ADJ National Semiconductor, LM2641MTC-ADJ Datasheet - Page 12

• Manufacturer Part Number: LM2641MTC-ADJ
• Description: Power Supply IC
• Manufacturer: National Semiconductor

Specifications of LM2641MTC-ADJ

• Power Dissipation Pd: 883mW
• No. Of Pins: 28
• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

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Application Information
SYNC Pin
The basic operating frequency of 300kHz can be increased
to up to 400kHz by using the SYNC pin and an external
CMOS or TTL clock. The synchronizing pulses must have a
minimum pulse width of 200 ns.
If the sync function is not used, the SYNC pin must be con-
nected to the LIN pin or to ground to prevent false triggering.
Current Limit Circuitry
The LM2641 is protected from damage due to excessive out-
put current by an internal current limit comparator, which
monitors output current on a cycle-by-cycle basis. The cur-
rent limiter activates when ever the absolute magnitude of
the voltage developed across the output sense resistor ex-
ceeds 100 mV (positive or negative value).
If the sensed voltage exceeds 100 mV, the high-side FET
switch is turned OFF. If the sensed voltage goes below -100
mV, the low-side FET switch is turned OFF. It should be
noted that drawing sufficient output current to activate the
current limit circuits can cause the output voltage to drop,
which could result in a under-voltage latch-OFF condition
(see next section).
Under-voltage/Over-voltage Protection
The LM2641 contains protection circuitry which activates if
the output voltage is too low (UV) or too high (OV). In the
event of either a UV or OV fault, the LM2641 is latched off
and the high-side FET is turned off, while the low-side FET is
turned on.
If the output voltage drops below 70% of nominal value, the
under-voltage comparator will latch OFF the LM2641. To re-
store operation, power to the device must be shut off and
then restored.
It should be noted that the UV latch provides protection in
cases where excessive output current forces the output volt-
age down. The UV latch circuitry is disabled during start-up.
If the output voltage exceeds 150% of nominal, the
over-voltage comparator latches off the LM2641. As stated
before, power must be cycled OFF and then ON to restore
operation.
It must be noted that the OV latch can not protect the load
from damage in the event of a high-side FET switch failure
(where the FET shorts out and connects the input voltage to
the load).
Protection for the load in the event of such a failure can be
implemented using a fuse in the power lead. Since the
low-side FET switch turns ON whenever the OV latch acti-
vates, this would blow a series fuse if the FET and fuse are
correctly sized.
Soft-Start
An internal 5 µA current source connected to the soft-start
pins allows the user to program the turn-on time of the
LM2641. If a capacitor is connected to the SS pin, the volt-
age at that pin will ramp up linearly at turn ON. This voltage
is used to control the pulse widths of the FET switches.
The pulse widths start at a very narrow value and linearly in-
crease up to the point where the SS pin voltage is about
1.3V. At that time, the pulse-to-pulse current limiter controls
the pulse widths until the output reaches its nominal value
(and the PWM current-mode control loop takes over).
(Continued)
12
The LM2641 contains a digital counter (referenced to the os-
cillator frequency) that times the soft-start interval. The maxi-
mum allotted SS time period is 4096 counts of the oscillator
clock, which means the time period varies with oscillator fre-
quency:
If the output voltage does not move to within −1% of nominal
in the period of 4096 counts, the device will latch OFF. To re-
store operation, the power must be cycled OFF to ON.
Minimum Pulse Width
As the input voltage is increased, the pulse widths of the
switching FET’s decreases. If the pulse widths become nar-
rower than 350ns, pulse jitter may occur as the pulses alter-
nate with slightly different pulse widths. This is does not af-
fect regulator stability or output voltage accuracy.
Loop Compensation
The LM2641 must be properly compensated to assure
stable operation and good transient response. As with any
control loop, best performance is achieved when the com-
pensation is optimized so that maximum bandwidth is ob-
tained while still maintaining sufficient phase margin for good
stability.
Best performance for the LM2641 is typically obtained when
the loop bandwidth (defined as the frequency where the loop
gain equals unity) is in the range of F
In the discussion of loop stability, it should be noted that
there is a high-frequency pole f
be approximated by:
f
Where:
As can be seen in the approximation for Q
quency for f
lowest frequency for f
4.5V and V
As noted above, the location of the pole f
the range of about F
near the unity-gain crossover frequency, and it can signifi-
cantly reduce phase margin if left uncompensated. Fortu-
nately, the ESR of the output capacitor(s) forms a zero which
is usually very near the frequency of f
cancellation of the negative phase shift it would otherwise
cause. For this reason, the output capacitor must be care-
fully selected.
Most of the loop compensation for the LM2641 is set by an
R-C network from the output of the error amplifier to ground
(see Figure 4 ). Since this is a transconductance amplifier, it
has a very high output impedance (160 k ).
p
(HF)
max. allowable SS interval = 4096 / F
F
OSC
OUT
p
(HF) occurs at the maximum value of V
/2 X Q
= 1.8V).
OSC
S
p
(Assumes Q
(HF) is about F
/10 to F
p
OSC
(HF), whose frequency can
S
/4. This pole will often be
<
OSC
OSC
0.5)
p
(HF), and provides
p
/10 to F
(HF) is typically in
S
/10 (when V
, the highest fre-
OSC
OSC
IN
/5.
. The
IN
=