LM5642XMT National Semiconductor, LM5642XMT Datasheet - Page 3
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LM5642XMT
Manufacturer Part Number
LM5642XMT
Description
IC,SMPS CONTROLLER,CURRENT-MODE,TSSOP,28PIN,PLASTIC
Manufacturer
National Semiconductor
Specifications of LM5642XMT
Rohs Compliant
NO
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CBOOT2 (Pin 18): Bootstrap capacitor connection. It serves
as the positive supply rail for the Channel 2 top-side gate
drive. Connect this pin to VDD2 (Pin 19) through a diode, and
connect the low side of the bootstrap capacitor to SW2
(Pin16).
VDD2 (Pin 19): The supply rail for the Channel 2 low-side
gate drive. Connected to VLIN5 (Pin 7) through a 4.7Ω resis-
tor and bypassed to power ground with a ceramic capacitor
of at least 1µF. Tie this pin to VDD1 (Pin 24).
LDRV2 (Pin 20): Low-side gate-drive output for Channel 2.
PGND (Pin 21): The power ground connection for both chan-
nels. Connect to the ground rail of the system.
VIN (Pin 22): The power input pin for the chip. Connect to the
positive (+) input rail of the system. This pin must be con-
nected to the same voltage rail as the top FET drain (or the
current sense resistor when used).
LDRV1 (Pin 23): Low-side gate-drive output for Channel 1.
3
VDD1 (Pin 24): The supply rail for Channel 1 low-side gate
drive. Tie this pin to VDD2 (Pin 19).
CBOOT1 (Pin 25): : Bootstrap capacitor connection. This pin
serves as the positive supply rail for the Channel 1 top-side
gate drive. See CBOOT2 (Pin 18).
HDRV1 (Pin 26): Top-side gate-drive output for Channel 1.
See HDRV2 (Pin 17).
SW1 (Pin 27): Switch-node connection for Channel 1. See
SW2 (Pin16).
RSNS1 (Pin 28): The negative (-) Kelvin sense for the internal
current sense amplifier of Channel 1. See RSNS2 (Pin 15).
PGND (DAP): The power ground connection for both chan-
nels. Connect to the ground rail of the system. Use of multiple
vias to internal ground plane or GND layer helps to dissipate
heat generated by output power.
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