LM82CIMQA National Semiconductor, LM82CIMQA Datasheet - Page 11

• Manufacturer Part Number: LM82CIMQA
• Description: IC,SSOP,16PIN
• Manufacturer: National Semiconductor

Specifications of LM82CIMQA

• Rohs Compliant: NO

1.0 Functional Description
1.9 COMMUNICATING with the LM82
There are 13 data registers in the LM82, selected by the
Command Register. At power-up the Command Register is
set to “00”, the location for the Read Local Temperature
Register. The Command Register latches the last location it
was set to. Reading the Status Register resets T_CRIT_A
and INT, so long as a temperature comparison does not
signal a fault (see Sections 1.2 and 1.3). All other registers
are predefined as read only or write only. Read and write
registers with the same function contain mirrored data.
A Write to the LM82 will always include the address byte and
the command byte. A write to any register requires one data
byte.
Reading the LM82 can take place either of two ways:
1. If the location latched in the Command Register is cor-
2. If the Command Register needs to be set, then an
rect (most of the time it is expected that the Command
Register will point to one of the Read Temperature Reg-
isters because that will be the data most frequently read
from the LM82), then the read can simply consist of an
address byte, followed by retrieving the data byte.
address byte, command byte, repeat start, and another
(Continued)
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The data byte has the most significant bit first. At the end of
a read, the LM82 can accept either Acknowledge or No
Acknowledge from the Master (No Acknowledge is typically
used as a signal for the slave that the Master has read its
last byte).
1.10 SERIAL INTERFACE ERROR RECOVERY
The LM82 SMBus lines will be reset to the SMBus idle state
if the SMBData or SMBCLK lines are held low for 40 ms or
more (t
the serial interface logic if either of the SMBData or SMBCLK
lines are held low between 25 ms and 40 ms. TIMEOUT
allows a clean recovery in cases where the master may be
reset while the LM82 is transmitting a low bit thus preventing
possible bus lock up.
Whenever the LM82 sees the start condition its serial inter-
face will reset to the beginning of the communication, thus
the LM82 will expect to see an address byte next. This
simplifies recovery when the master is reset while the LM82
is transmitting a high.
address byte will accomplish a read.
TIMEOUT
). The LM82 may or may not reset the state of
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