LM96000CIMT National Semiconductor, LM96000CIMT Datasheet - Page 25

• Manufacturer Part Number: LM96000CIMT
• Description: IC,Data Acquisition System,7-CHANNEL,8-BIT,TSSOP,24PIN,PLASTIC
• Manufacturer: National Semiconductor

Specifications of LM96000CIMT

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Register
Address
74h
Register
Address
6Fh
Functional Description
These registers become Read Only when the Ready/Lock/Start/Override register Lock bit is set. Any further attempts to write to
thses registers shall have no effect. After power up the default value is used whenever the Ready/Lock/Start/Override register
Start bit is cleared even though modifications to this register are possible.
4.21 Register 6Fh: Test Register
If the XEN bit is set high, the part will be placed into XOR tree test mode. Clearing the bit (writing a 0 to the XEN bit) brings the
part out of XOR tree test mode.
This register becomes Read Only when the Ready/Lock/Start/Override register Lock bit is set. Any further attempts to write to this
registers shall have no effect. After power up the default value is used whenever the Ready/Lock/Start/Override register Start bit
is cleared even though modifications to this register are possible.
4.22 Registers 70-7Fh: Vendor Specific Registers
These registers are for vendor specific features, including test registers. They will not default to a specific value on power up.
4.22.1 Register 74h: Tachometer Monitor Mode
Each fan TACH input has 4 possible modes of operation when using the low frequency range for the PWM outputs. Mode 0 is the
only mode that is available when using the high frequecy range for the PWM outputs. The modes for TACH3 and TACH4 share
control bits T3/4-[1:0]; TACH2 is controlled by T2-[1:0]; TACH1 is controlled by T1-[1:0]. The result reported in all modes is based
on 2 pulses per revolution. In order for modes 2 and 3 to function properly it is required that the:
• Mode 0: This mode uses the conventional method for fan tachometer pulse detection and does not include any circuitry to
• Mode 1: This mode uses the conventional method for fan tach detection. The reading will be FFFFh if it is below minimum
Setting (Tn[1:0]) Mode Function
PWM1 output must control the fan that has it’s tachometer output connected to the TACH1 LM96000 input.
PWM2 output must control the fan that has it’s tachometer output connected to the TACH2 LM96000 input.
PWM3 output must control the fans that have their tachometer outputs connected to the TACH3 or TACH4 LM96000 inputs.
compensate for PWM Fan drive. This mode should be used when PWM drive is not used to power the fan. This mode may
report a false RPM reading when under minimum detectable RPM as shown in the following table.
detectable RPM.
– The fan will remain on, at Fan PWM Minimum, until the temperature goes a certain amount below Fan Temp Limit.
– The Hysteresis registers control this amount. See below table for details.
00
01
10
11
Read/
R/W
Write
Read/
Write
R/W
Tach Monitor Mode
0
1
2
3
Register
Name
Test Register
Register
Name
Traditional tach input monitor, false readings when under minimum detctable RPM
Traditional tach input monitor, FFFFh reading when under minimum detectable RPM
Most accurate readings, FFFFh reading when under minimum detectable RPM
Least effect on programmed PWM of Fan, FFFFh reading when under minimum detectable RPM
(Continued)
Bit 7
(MSB)
RES
(MSb)
RES
Bit 7
Setting
Fh
0h
5h
TABLE 12. Hysteresis Settings
.
.
.
.
.
.
Bit 6
RES
Bit 6
RES
T3/4-1
Bit 5
Bit 5
RES
25
T3/4-0
Bit 4
HYSTERESIS
Bit 4
RES
15˚C
0˚C
5˚C
.
.
.
.
.
.
Bit 3
T2-1
Bit 3
RES
Bit 2
T2-0
Bit 2
RES
Bit 1
T1-1
Bit 1
RES
(LSb)
T1-0
Bit 0
Bit 0
(LSB)
XEN
Default
00h
Value
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Default
Value
00h
Lock?