LMV712LD National Semiconductor, LMV712LD Datasheet - Page 11

• Manufacturer Part Number: LMV712LD
• Description: IC,Operational Amplifier,DUAL,BICMOS,LLCC,10PIN,PLASTIC
• Manufacturer: National Semiconductor

Specifications of LMV712LD

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Application Information
In Figure 3 , the isolation resistor R
C
margin to the overall system. The desired performance de-
pends on the value of R
value, the more stable V
degraded when the R
resistor in Figure 3 , the output voltage would be divided by
R
The circuit in Figure 4 is an improvement to the one in Figure
3 because it provides DC accuracy as well as AC stability. In
this circuit, R
feed-forward techniques to connect V
serve to counteract the loss of phase margin by feeding the
high frequency component of the output signal back to the
amplifier’s inverting input, thereby preserving phase margin
L
ISO
form a pole to increase stability by adding more phase
and the load resistor.
F
provides the DC accuracy by using
ISO
FIGURE 3.
OUT
ISO
gets bigger. If there were a load
. The bigger the R
will be. But the DC accuracy is
ISO
and the load capacitor
IN
to R
(Continued)
10137032
L
. C
ISO
F
and R
resistor
ISO
11
in the overall feedback loop. Increased capacitive drive is
possible by increasing the value of C
down the pulse response.
Latchup
CMOS devices tend to be susceptible to latchup due to their
internal parasitic SCR (silicon controlled rectifier) effects.
The input and output pins look similar to the gate of the SCR.
There is a minimum current required to trigger the SCR gate
lead. The LMV712 is designed to withstand 150mA surge
current on all the pins. Some resistive method should be
used to isolate any capacitance from supplying excess cur-
rent to the pins. In addition, like an SCR, there is a minimum
holding current for any latchup mode. Limiting current to the
supply pins will also inhibit latchup susceptibility.
FIGURE 4.
F
. This in turn will slow
10137033
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