LP2995MR National Semiconductor, LP2995MR Datasheet - Page 8

• Manufacturer Part Number: LP2995MR
• Description: Voltage Regulator IC
• Manufacturer: National Semiconductor

Specifications of LP2995MR

• No. Of Pins: 8
• Peak Reflow Compatible (260 C): No
• Supply Voltage Max: 5V
• Leaded Process Compatible: No
• Package / Case: 8-PSOP
• Output Current Max: 1500A
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

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Component Selection
the best solution when size and performance are critical,
although their cost is typically higher than any other capaci-
tor.
Capacitor recommendations for different application circuits
can be seen in the accompanying application notes with
supporting evaluation boards.
Thermal Dissipation
Since the LP2995 is a linear regulator any current flow from
V
To prevent damaging the part from exceeding the maximum
allowable junction temperature, care should be taken to
derate the part dependent on the maximum expected ambi-
ent temperature and power dissipation. The maximum allow-
able internal temperature rise (T
given the maximum ambient temperature (T
application and the maximum allowable junction temperature
(T
From this equation, the maximum power dissipation (P
of the part can be calculated:
The θ
ables: the package used; the thickness of copper; the num-
ber of vias and the airflow. For instance, the θ
is 163˚C/W with the package mounted to a standard 8x4
2-layer board with 1oz. copper, no airflow, and 0.5W dissi-
pation at room temperature. This value can be reduced to
151.2˚C/W by changing to a 3x4 board with 2 oz. copper that
is the JEDEC standard. Figure 2 shows how the θ
with airflow for the two boards mentioned.
Layout is also extremely critical to maximize the output
current with the LLP package. By simply placing vias under
TT
Jmax
will result in internal power dissipation generating heat.
JA
).
of the LP2995 will be dependent on several vari-
FIGURE 2. θ
T
Rmax
P
Dmax
= T
JA
= T
Jmax
vs Airflow (SO-8)
Rmax
− T
Rmax
/ θ
Amax
JA
(Continued)
) can be calculated
JA
Amax
of the SO-8
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JA
) of the
varies
Dmax
)
8
the DAP the θ
the LLP thermal data when placed on a 4-layer JEDEC
board with copper thickness of 0.5/1/1/0.5 oz. The number of
vias, with a pitch of 1.27 mm, has been increased to the
maximum of 4 where a θ
Via wall thickness for this calculation is 0.036 mm for 1oz.
Copper.
Additional improvements in lowering the θ
achieved with a constant airflow across the package. Main-
taining the same conditions as above and utilizing the 2x2
via array, Figure 4 shows how the θ
FIGURE 4. θ
FIGURE 3. LLP-16 θ
JA
JA
can be lowered significantly. Figure 3 shows
vs Airflow Speed (JEDEC Board with 4
JA
JA
Board))
vs # of Vias (4 Layer JEDEC
Vias)
of 50.41˚C/W can be obtained.
JA
varies with airflow.
JA
can also be
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