PIC12F635-E/SN Microchip Technology, PIC12F635-E/SN Datasheet - Page 105
PIC12F635-E/SN
Manufacturer Part Number
PIC12F635-E/SN
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,8PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 12Fr
Specifications of PIC12F635-E/SN
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
5
Program Memory Size
1.75KB (1K x 14)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
8-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162057 - MPLAB ICD 2 HEADER 14DIP
Data Converters
-
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC12F635-E/SN
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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- Download datasheet (4Mb)
PIC12F635/PIC16F636/639
11.15 Configurable Output Enable Filter
The purpose of this filter is to enable the LFDATA output
and wake the microcontroller only after receiving a
specific sequence of pulses on the LC input pins.
Therefore, it prevents the AFE from waking up the
microcontroller due to noise or unwanted input signals.
The circuit compares the timing of the demodulated
header waveform with a pre-defined value, and enables
the demodulated LFDATA output when a match occurs.
The output enable filter consists of a high (T
) and
OEH
low duration (T
) of a pulse immediately after the
OEL
AGC settling gap time. The selection of high and low
times further implies a max period time. The output
enable high and low times are determined by SPI
interface programming. Figure 11-5 and Figure 11-6
show the output enable filter waveforms.
There should be no missing cycles during T
.
OEH
Missing cycles may result in failing the output enable
condition.
FIGURE 11-5:
OUTPUT ENABLE FILTER TIMING
Required Output Enable Sequence
Data Packet
T
STAB
(T
+ T
)
AGC
PAGC
Demodulator
T
GAP
Output
t
T
t
T
OEL
OEH
Start bit
AGC
AFE
Wake-up
Gap Pulse
LFDATA output is enabled
and AGC Stabilization
t
T
OET
on this rising edge
© 2007 Microchip Technology Inc.
DS41232D-page 103
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