PIC12F675T-E/SN Microchip Technology, PIC12F675T-E/SN Datasheet - Page 40
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PIC12F675T-E/SN
Manufacturer Part Number
PIC12F675T-E/SN
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,8PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 12Fr
Datasheets
1.PIC12F629T-ISN.pdf
(136 pages)
2.PIC12F629T-ISN.pdf
(8 pages)
3.PIC12F629T-ISN.pdf
(24 pages)
Specifications of PIC12F675T-E/SN
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Size
1.75KB (1K x 14)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
8-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PIC12F675-E/SNTR
PIC12F675T-E/SNTR
PIC12F675T-E/SNTR
PIC12F675T-E/SNTR
PIC12F675T-E/SNTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC12F675T-E/SN
Manufacturer:
MICROCHIP
Quantity:
12 000
Part Number:
PIC12F675T-E/SN
Manufacturer:
MICROCHI
Quantity:
20 000
PIC12F629/675
6.3
A simplified circuit for an analog input is shown in
Figure 6-3. Since the analog pins are connected to a
digital output, they have reverse biased diodes to V
and V
V
FIGURE 6-3:
6.4
The comparator output, COUT, is read through the
CMCON register. This bit is read-only. The comparator
output may also be directly output to the GP2 pin in
three of the eight possible modes, as shown in
Figure 6-2. When in one of these modes, the output on
GP2 is asynchronous to the internal clock. Figure 6-4
shows the comparator output block diagram.
FIGURE 6-4:
DS41190G-page 40
SS
and V
SS
. The analog input, therefore, must be between
Analog Input Connection
Considerations
Comparator Output
To GP2/T0CKI pin
DD
. If the input voltage deviates from this
VA
Legend:
To Data Bus
Rs < 10K
Set CMIF bit
ANALOG INPUT MODE
MODIFIED COMPARATOR OUTPUT BLOCK DIAGRAM
RD CMCON
A
IN
C
V
I
R
R
VA
LEAKAGE
T
PIN
IC
S
C
5 pF
PIN
= Input Capacitance
= Threshold Voltage
= Leakage Current at the pin due to Various Junctions
= Interconnect Resistance
= Source Impedance
= Analog Voltage
Q
Q
DD
V
DD
EN
EN
V
V
D
D
T
T
= 0.6V
= 0.6V
Reset
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up may occur. A
maximum
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
The TRISIO<2> bit functions as an output enable/
disable for the GP2 pin while the comparator is in an
Output mode.
RD CMCON
Note 1: When reading the GPIO register, all pins
2: Analog levels on any pin that is defined as
Leakage
±500 nA
Vss
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert an analog input according to the
TTL input specification.
a digital input, may cause the input buffer
to consume more current than is
specified.
source
CINV
R
IC
impedance
2010 Microchip Technology Inc.
CM2:CM0
GP0/CIN+
GP1/CIN-
CV
of
REF
10 k
is