PIC16F631T-I/SS Microchip Technology, PIC16F631T-I/SS Datasheet - Page 204
![IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SSOP,20PIN,PLASTIC](/photos/6/58/65895/150-20-ssop_sml.jpg)
PIC16F631T-I/SS
Manufacturer Part Number
PIC16F631T-I/SS
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SSOP,20PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F690DM-PCTLHS.pdf
(306 pages)
3.PIC16F677-IP.pdf
(2 pages)
4.PIC16F677-IP.pdf
(16 pages)
Specifications of PIC16F631T-I/SS
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
18
Program Memory Size
1.75KB (1K x 14)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
658-1047-5 - BOARD EVALUATION ACCESSTOUCHXLT20SS1-1 - SOCKET TRANSITION 20DIP 20SSOPAC162061 - HEADER INTRFC MPLAB ICD2 20PIN
Data Converters
-
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F631T-I/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC16F690DM-PCTLHS PDF datasheet #2
- PIC16F677-IP PDF datasheet #3
- PIC16F677-IP PDF datasheet #4
- Current page: 204 of 306
- Download datasheet (6Mb)
PIC16F631/677/685/687/689/690
14.2.4
The BOREN0 and BOREN1 bits in the Configuration
Word register select one of four BOR modes. Two
modes have been added to allow software or hardware
control of the BOR enable. When BOREN<1:0> = 01,
the SBOREN bit (PCON<4>) enables/disables the
BOR allowing it to be controlled in software. By
selecting BOREN<1:0>, the BOR is automatically
disabled in Sleep to conserve power and enabled on
wake-up. In this mode, the SBOREN bit is disabled.
See
definition.
If V
(T
the Brown-out situation will reset the device. This will
occur regardless of V
to occur if V
(T
FIGURE 14-3:
DS41262E-page 202
BOR
BOR
DD
) (see Section 17.0 “Electrical Specifications”),
).
Register 14-2
Note 1: 64 ms delay only if PWRTE bit is programmed to ‘0’.
falls below V
DD
BROWN-OUT RESET (BOR)
falls below V
Internal
Internal
Internal
Reset
Reset
Reset
V
V
V
DD
DD
DD
DD
BOR
for
BROWN-OUT SITUATIONS
slew rate. A Reset is not insured
for greater than parameter
BOR
the
for less than parameter
Configuration
Word
< 64 ms
64 ms
On any Reset (Power-on, Brown-out Reset, Watchdog
Timer, etc.), the chip will remain in Reset until V
above V
will now be invoked, if enabled and will keep the chip in
Reset an additional 64 ms.
If V
running, the chip will go back into a Brown-out Reset
and the Power-up Timer will be re-initialized. Once V
rises above V
64 ms Reset.
(1)
Note:
64 ms
64 ms
DD
drops below V
(1)
BOR
(1)
The Power-up Timer is enabled by the
PWRTE bit in the Configuration Word
register.
(see Figure 14-3). The Power-up Timer
BOR
, the Power-up Timer will execute a
BOR
© 2008 Microchip Technology Inc.
while the Power-up Timer is
V
V
V
BOR
BOR
BOR
DD
rises
DD
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