PIC16F636T-I/ML Microchip Technology, PIC16F636T-I/ML Datasheet - Page 141
![IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,16PIN,PLASTIC](/photos/6/65/66536/mfg_mcp7386x_qfn_sml.jpg)
PIC16F636T-I/ML
Manufacturer Part Number
PIC16F636T-I/ML
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,16PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC12F635-ISN.pdf
(234 pages)
3.PIC16F636-ISL.pdf
(8 pages)
4.PIC16F636-ISL.pdf
(4 pages)
Specifications of PIC16F636T-I/ML
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, LVD, POR, WDT
Number Of I /o
11
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-QFN
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
RS- 232, SPI, USB
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNXLT16QFN1 - SOCKET TRANSITION 14DIP TO 16QFNAC162057 - MPLAB ICD 2 HEADER 14DIP
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Details
- PIC16F616T-ISL PDF datasheet
- PIC12F635-ISN PDF datasheet #2
- PIC16F636-ISL PDF datasheet #3
- PIC16F636-ISL PDF datasheet #4
- Current page: 141 of 234
- Download datasheet (4Mb)
12.9
The PIC12F635/PIC16F636/639 has multiple interrupt
sources:
• External Interrupt RA2/INT
• Timer0 Overflow Interrupt
• PORTA Change Interrupts
• 2 Comparator Interrupts
• Timer1 Overflow Interrupt
• EEPROM Data Write Interrupt
• Fail-Safe Clock Monitor Interrupt
The Interrupt Control register (INTCON) and Peripheral
Interrupt Request Register 1 (PIR1) record individual
interrupt requests in flag bits. The INTCON register
also has individual and global interrupt enable bits.
A Global Interrupt Enable bit GIE of the INTCON regis-
ter enables (if set) all unmasked interrupts, or disables
(if cleared) all interrupts. Individual interrupts can be
disabled through their corresponding enable bits in the
INTCON register and PIE1 register. GIE is cleared on
Reset.
The Return from Interrupt instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables unmasked interrupts.
The following interrupt flags are contained in the
INTCON register:
• INT Pin Interrupt
• PORTA Change Interrupt
• TMR0 Overflow Interrupt
The peripheral interrupt flags are contained in the
special register, PIR1. The corresponding interrupt
enable bit is contained in special register, PIE1.
The following interrupt flags are contained in the PIR1
register:
• EEPROM Data Write Interrupt
• 2 Comparator Interrupts
• Timer1 Overflow Interrupt
• Fail-Safe Clock Monitor Interrupt
When an interrupt is serviced:
• The GIE is cleared to disable any further interrupt.
• The return address is pushed onto the stack.
• The PC is loaded with 0004h.
© 2007 Microchip Technology Inc.
Interrupts
PIC12F635/PIC16F636/639
For external interrupt events, such as the INT pin or
PORTA change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends upon when the interrupt event occurs (see
Figure 12-8). The latency is the same for one or
two-cycle instructions. Once in the Interrupt Service
Routine, the source(s) of the interrupt can be
determined by polling the interrupt flag bits. The
interrupt flag bit(s) must be cleared in software before
re-enabling interrupts to avoid multiple interrupt
requests.
For additional information on Timer1, comparators or
data EEPROM modules, refer to the respective
peripheral section.
12.9.1
External interrupt on RA2/INT pin is edge-triggered;
either rising if the INTEDG bit of the OPTION register is
set, or falling if the INTEDG bit is clear. When a valid
edge appears on the RA2/INT pin, the INTF bit of the
INTCON register is set. This interrupt can be disabled
by clearing the INTE control bit of the INTCON register.
The INTF bit must be cleared in software in the Interrupt
Service Routine before re-enabling this interrupt. The
RA2/INT interrupt can wake-up the processor from
Sleep if the INTE bit was set prior to going into Sleep.
The status of the GIE bit decides whether or not the
processor branches to the interrupt vector following
wake-up (0004h). See Section 12.12 “Power-Down
Mode (Sleep)” for details on Sleep and Figure 12-10 for
timing of wake-up from Sleep through RA2/INT interrupt.
Note:
Note 1: Individual interrupt flag bits are set,
2: When an instruction that clears the GIE
RA2/INT INTERRUPT
The CMCON0 (19h) register must be
initialized to configure an analog channel
as a digital input. Pins configured as
analog inputs will read ‘0’.
regardless
corresponding mask bit or the GIE bit.
bit is executed, any interrupts that were
pending for execution in the next cycle
are ignored. The interrupts, which were
ignored, are still pending to be serviced
when the GIE bit is set again.
of
the
DS41232D-page 139
status
of
their
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