PIC16F685-E/ML Microchip Technology, PIC16F685-E/ML Datasheet - Page 177
![IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,20PIN,PLASTIC](/photos/6/64/66481/c04-126_ml_sml.jpg)
PIC16F685-E/ML
Manufacturer Part Number
PIC16F685-E/ML
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,20PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F690DM-PCTLHS.pdf
(306 pages)
3.PIC16F677-IP.pdf
(2 pages)
4.PIC16F677-IP.pdf
(16 pages)
Specifications of PIC16F685-E/ML
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNAC162061 - HEADER INTRFC MPLAB ICD2 20PINDVA1004 - DEVICE ADAPTER 8/14/20DIP
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F685-E/ML
Manufacturer:
DM&P
Quantity:
27
- PIC16F616T-ISL PDF datasheet
- PIC16F690DM-PCTLHS PDF datasheet #2
- PIC16F677-IP PDF datasheet #3
- PIC16F677-IP PDF datasheet #4
- Current page: 177 of 306
- Download datasheet (6Mb)
12.4.2
The following bits are used to configure the EUSART
for Synchronous slave operation:
• SYNC = 1
• CSRC = 0
• SREN = 0 (for transmit); SREN = 1 (for receive)
• CREN = 0 (for transmit); CREN = 1 (for receive)
• SPEN = 1
Setting the SYNC bit of the TXSTA register configures the
device for synchronous operation. Clearing the CSRC bit
of the TXSTA register configures the device as a slave.
Clearing the SREN and CREN bits of the RCSTA register
ensures that the device is in the Transmit mode,
otherwise the device will be configured to receive. Setting
the SPEN bit of the RCSTA register enables the
EUSART. If the RX/DT or TX/CK pins are shared with an
analog peripheral the analog I/O functions must be
disabled by clearing the corresponding ANSEL bits.
12.4.2.1
The operation of the Synchronous Master and Slave
modes
“Synchronous Master Transmission”), except in the
case of the Sleep mode.
TABLE 12-9:
© 2008 Microchip Technology Inc.
BAUDCTL ABDOVF
INTCON
PIE1
PIR1
RCREG
RCSTA
SPBRG
SPBRGH
TRISB
TXREG
TXSTA
Legend:
Name
are
x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Transmission.
SYNCHRONOUS SLAVE MODE
EUSART Receive Data Register
EUSART Transmit Data Register
TRISB7
BRG15
CSRC
EUSART Synchronous Slave
Transmit
SPEN
BRG7
Bit 7
GIE
—
—
identical
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
TRISB6
BRG14
RCIDL
BRG6
PEIE
ADIE
ADIF
Bit 6
RX9
TX9
(see
TRISB5
BRG13
SREN
BRG5
TXEN
RCIE
RCIF
Bit 5
T0IE
—
PIC16F631/677/685/687/689/690
Section 12.4.1.3
TRISB4
BRG12
CREN
SCKP
BRG4
SYNC
INTE
Bit 4
TXIE
TXIF
ADDEN
SENDB
BRG16
BRG11
RABIE
SSPIE
SSPIF
BRG3
Bit 3
CCP1IE
CCP1IF
BRG10
BRGH
FERR
BRG2
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
1.
2.
3.
4.
5.
12.4.2.2
1.
2.
3.
4.
5.
6.
7.
Bit 2
T0IF
—
The first character will immediately transfer to
the TSR register and transmit.
The second word will remain in TXREG register.
The TXIF bit will not be set.
After the first character has been shifted out of
TSR, the TXREG register will transfer the second
character to the TSR and the TXIF bit will now be
set.
If the PEIE and TXIE bits are set, the interrupt
will wake the device from Sleep and execute the
next instruction. If the GIE bit is also set, the
program will call the Interrupt Service Routine.
Set the SYNC and SPEN bits and clear the
CSRC bit.
Clear the CREN and SREN bits.
If interrupts are desired, set the TXIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
If 9-bit transmission is desired, set the TX9 bit.
Enable transmission by setting the TXEN bit.
If 9-bit transmission is selected, insert the Most
Significant bit into the TX9D bit.
Start
Significant 8 bits to the TXREG register.
TMR2IE
TMR2IF
OERR
BRG1
BRG9
TRMT
WUE
Bit 1
INTF
transmission
Synchronous Slave Transmission
Set-up:
TMR1IE
TMR1IF
ABDEN
RABIF
BRG0
BRG8
RX9D
TX9D
Bit 0
by
01-0 0-00
0000 000x
-000 0000
-000 0000
0000 0000
0000 000x
0000 0000
0000 0000
1111 ----
0000 0000
0000 0010
POR, BOR
Value on
writing
DS41262E-page 175
the
01-0 0-00
0000 000x
-000 0000
-000 0000
0000 0000
0000 000x
0000 0000
0000 0000
1111 ----
0000 0000
0000 0010
Value on
all other
Resets
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