PIC16F818-E/SO Microchip Technology, PIC16F818-E/SO Datasheet - Page 261
PIC16F818-E/SO
Manufacturer Part Number
PIC16F818-E/SO
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,18PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F818-ISO.pdf
(176 pages)
4.PIC16F818-ISO.pdf
(6 pages)
5.PIC16F818-ISO.pdf
(8 pages)
6.PIC16F818-ISO.pdf
(8 pages)
Specifications of PIC16F818-E/SO
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
1.75KB (1K x 14)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
18-SOIC (7.5mm Width)
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
I2C, SPI, SSP
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
16
Number Of Timers
1 x 16 bit
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014
Minimum Operating Temperature
- 40 C
On-chip Adc
5 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F818-E/SO
Manufacturer:
Microchip Technology
Quantity:
135
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F818-ISO PDF datasheet #3
- PIC16F818-ISO PDF datasheet #4
- PIC16F818-ISO PDF datasheet #5
- PIC16F818-ISO PDF datasheet #6
- Current page: 261 of 688
- Download datasheet (3Mb)
16.3.5
1997 Microchip Technology Inc.
SSPIF
Interrupt flag
SCK
(CKP = 0)
SCK
(CKP = 1)
Slave Operation
SDO
SDI
In slave mode, the data is transmitted and received as the external clock pulses appear on SCK.
When the last bit is latched the SSPIF interrupt flag bit is set.
The clock polarity is selected by appropriately programming the CKP bit (SSPCON<4>). This
then would give waveforms for SPI communication as shown in
where the MSb is transmitted first. When in slave mode the external clock must meet the mini-
mum high and low times.
In sleep mode, the slave can transmit and receive data and wake the device from sleep if the
interrupt is enabled.
Figure 16-4: SPI Mode Waveform (Slave Mode w/o SS Control)
bit7
bit7
bit6
bit5
bit4
bit3
Section 16. BSSP
bit2
bit1
Figure 16-5
DS31016A-page 16-11
bit0
bit0
and
Next Q4 Cycle
Figure 16-5
after Q2
16
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