PIC16F819-I/PTSL Microchip Technology, PIC16F819-I/PTSL Datasheet - Page 65
PIC16F819-I/PTSL
Manufacturer Part Number
PIC16F819-I/PTSL
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,DIP,18PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F818-ISO.pdf
(176 pages)
4.PIC16F818-ISO.pdf
(6 pages)
5.PIC16F818-ISO.pdf
(8 pages)
6.PIC16F818-ISO.pdf
(8 pages)
Specifications of PIC16F819-I/PTSL
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
18-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F818-ISO PDF datasheet #3
- PIC16F818-ISO PDF datasheet #4
- PIC16F818-ISO PDF datasheet #5
- PIC16F818-ISO PDF datasheet #6
- Current page: 65 of 688
- Download datasheet (3Mb)
1997 Microchip Technology Inc.
bit 7
bit 6:5
bit 4
bit 3
bit2
bit 1
bit 0
The STATUS register contains two bits (TO and PD), which when used in conjunction with the
PCON register bits provide the user with enough information to determine the cause of the reset.
Register 3-2: STATUS Register
bit 7
IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
For devices with only Bank0 and Bank1 the IRP bit is reserved, always maintain this bit clear.
RP1:RP0: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes. For devices with only Bank0 and Bank1 the IRP bit is reserved,
always maintain this bit clear.
TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions) (for borrow the polarity
is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Legend
R = Readable bit
U = Unimplemented bit, read as ‘0’
R/W-0
Note:
IRP
For borrow the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register.
R/W-0
RP1
W = Writable bit
R/W-0
RP0
R-1
TO
- n = Value at POR reset
Section 3. Reset
R-1
PD
R/W-x
Z
R/W-x
DS31003A-page 3-15
DC
bit 0
R/W-x
C
3
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