PIC16F819-I/PTSL Microchip Technology, PIC16F819-I/PTSL Datasheet - Page 22

• Manufacturer Part Number: PIC16F819-I/PTSL
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,DIP,18PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F819-I/PTSL

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F818/819
2.2.2.5
This register contains the individual flag bits for the
peripheral interrupts.
REGISTER 2-5:
DS39598E-page 20
bit 7
bit 6
bit 5-4
bit 3
bit 2
bit 1
bit 0
PIR1 Register
PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 (ADDRESS 0Ch)
bit 7
Unimplemented: Read as ‘0’
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed
0 = The A/D conversion is not complete
Unimplemented: Read as ‘0’
SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit
1 = The SSP interrupt condition has occurred and must be cleared in software before returning
0 = No SSP interrupt condition has occurred
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode.
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Legend:
R = Readable bit
-n = Value at POR
U-0
—
from the Interrupt Service Routine. The conditions that will set this bit are a transmission/
reception has taken place.
R/W-0
ADIF
U-0
—
W = Writable bit
‘1’ = Bit is set
U-0
—
Note:
SSPIF
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE (INTCON<7>).
User software should ensure the appropri-
ate interrupt flag bits are clear prior to
enabling an interrupt.
CCP1IF
R/W-0
 2004 Microchip Technology Inc.
TMR2IF
x = Bit is unknown
R/W-0
TMR1IF
R/W-0
bit 0