PIC16LC63A-04I/SS Microchip Technology, PIC16LC63A-04I/SS Datasheet - Page 24
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PIC16LC63A-04I/SS
Manufacturer Part Number
PIC16LC63A-04I/SS
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SSOP,28PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Specifications of PIC16LC63A-04I/SS
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
7KB (4K x 14)
Program Memory Type
OTP
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Processor Series
PIC16LC
Core
PIC
Data Bus Width
8 bit
Data Ram Size
192 B
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
22
Number Of Timers
8
Operating Supply Voltage
2.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000, DM163022
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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PIC16C63A/65B/73B/74B
4.2.2.6
This register contains the individual enable bit for the
CCP2 peripheral interrupt.
REGISTER 4-6:
4.2.2.7
This register contains the CCP2 interrupt flag bit.
REGISTER 4-7:
DS30605C-page 24
bit 7-1
bit 0
bit 7-1
bit 0
PIE2 Register
PIR2 Register
PIE2 REGISTER (ADDRESS 8Dh)
PIR2 REGISTER (ADDRESS 0Dh)
Unimplemented: Read as '0'
CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
Legend:
R = Readable bit
-n = Value at POR
Unimplemented: Read as '0'
CCP2IF: CCP2 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 7
U-0
U-0
—
—
U-0
U-0
—
—
W = Writable bit
’1’ = Bit is set
W = Writable bit
’1’ = Bit is set
U-0
U-0
—
—
U-0
U-0
—
—
Note:
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit, or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt
U-0
U-0
—
—
.
U-0
U-0
—
—
2000 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
U-0
U-0
—
—
CCP2IE
CCP2IF
R/W-0
R/W-0
bit 0
bit 0
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