PIC16LC923-04I/L Microchip Technology, PIC16LC923-04I/L Datasheet - Page 75
![IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,68PIN,PLASTIC](/photos/12/13/121323/c04-049_l_sml.jpg)
PIC16LC923-04I/L
Manufacturer Part Number
PIC16LC923-04I/L
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,68PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheet
1.PIC16C923-04L.pdf
(189 pages)
Specifications of PIC16LC923-04I/L
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Connectivity
I²C, SPI
Peripherals
LCD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
7KB (4K x 14)
Program Memory Type
OTP
Ram Size
176 x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
68-PLCC
Processor Series
PIC16LC
Core
PIC
Data Bus Width
8 bit
Data Ram Size
176 B
Interface Type
I2C, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
25
Number Of Timers
3
Operating Supply Voltage
2.5 V to 6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16LC923-04I/L
Manufacturer:
Microchip Technology
Quantity:
10 000
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11.3.1.2
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT reg-
ister is cleared. The received address is loaded into the
SSPBUF register.
When the address byte overflow condition exists, then
no acknowledge (ACK) pulse is given. An overflow con-
dition is defined as either bit BF (SSPSTAT<0>) is set
or bit SSPOV (SSPCON<6>) is set.
FIGURE 11-19: I
SDA
SCL
SSPIF (PIR1<3>)
1997 Microchip Technology Inc.
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
S
RECEPTION
A7 A6 A5 A4 A3 A2 A1
1
2
Receiving Address
2
3
C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
4
5
6
7
R/W=0
8
ACK
9
D7
1
D6
2
SSPBUF register is read
Receiving Data
D5
3
Cleared in software
D4
Bit SSPOV is set because the SSPBUF register is still full.
4
D3
5
D2
6
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-
ware. The SSPSTAT register is used to determine the
status of the byte.
D1
7
D0
8
ACK
9
D7
1
D6
2
D5
Receiving Data
3
D4
4
ACK is not sent.
PIC16C9XX
D3
5
D2
6
D1
7
DS30444E - page 75
D0
8
ACK
9
Bus Master
terminates
transfer
P
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