PIC16LC924-04I/PT Microchip Technology, PIC16LC924-04I/PT Datasheet - Page 59

• Manufacturer Part Number: PIC16LC924-04I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC924-04I/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 176 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 6 V
• Data Converters: A/D 5x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.2.1
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
10.2.2
When Generate Software Interrupt is chosen, the
CCP1 pin is not affected. Only a CCP interrupt is gen-
erated (if enabled).
10.2.3
In this mode, an internal hardware trigger is generated
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair and starts an A/D conversion. This
allows the CCPR1H:CCPR1L register pair to effectively
be a 16-bit programmable period register for Timer1.
10.3
In Pulse Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTC data latch,
the TRISC<2> bit must be cleared to make the CCP1
pin an output.
Figure 10-4 shows a simplified block diagram of the
CCP module in PWM mode.
For a step by step procedure on how to set up the CCP
module for PWM operation, see Section 10.3.3.
1997 Microchip Technology Inc.
Note:
Note:
TIMER1 MODE SELECTION
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
PWM Mode
The "special event trigger" from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
FIGURE 10-4: SIMPLIFIED PWM BLOCK
A PWM output (Figure 10-5) has a time-base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
FIGURE 10-5: PWM OUTPUT
10.3.1
The PWM period is specified by writing to the PR2 reg-
ister. The PWM period can be calculated using the fol-
lowing formula:
PWM frequency is defined as 1 / [PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
• The PWM duty cycle is latched from CCPR1L into
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock
cycle = 0%, the CCP1 pin will not be set)
CCPR1H
PWM period = [ (PR2) + 1 ] • 4 • T
CCPR1L
CCPR1H (Slave)
Comparator
Duty cycle registers
PR2
TMR2 = PR2
or 2 bits of the prescaler to create 10-bit time-base.
TMR2
Comparator
PWM PERIOD
Duty Cycle
Period
(TMR2 prescale value)
DIAGRAM
(Note 1)
Clear Timer,
CCP1 pin and
latch D.C.
TMR2 = Duty Cycle
PIC16C9XX
TMR2 = PR2
CCP1CON<5:4>
R
S
DS30444E - page 59
OSC
Q
TRISC<2>
•
RC1/CCP1