PIC16LF870T-I/SS Microchip Technology, PIC16LF870T-I/SS Datasheet - Page 86
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PIC16LF870T-I/SS
Manufacturer Part Number
PIC16LF870T-I/SS
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SSOP,28PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Specifications of PIC16LF870T-I/SS
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC16F870/871
10.4
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D result register
pair will NOT be updated with the partially completed
A/D conversion sample. That is, the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers). After the A/D conversion
is aborted, a 2 T
FIGURE 10-3:
10.4.1
The ADRESH:ADRESL register pair is the location
where the 10-bit A/D result is loaded at the completion of
the A/D conversion. This register pair is 16-bits wide.
The A/D module gives the flexibility to left or right justify
the 10-bit result in the 16-bit result register. The A/D For-
FIGURE 10-4:
DS30569B-page 84
A/D Conversions
A/D RESULT REGISTERS
T
CY
Set GO bit
Holding capacitor is disconnected from analog input (typically 100 ns)
7
to T
0000 00
AD
ADRESH
AD
wait is required before the next
Conversion starts
A/D CONVERSION T
A/D RESULT JUSTIFICATION
T
AD
Right Justified
1
2 1 0 7
ADFM = 1
T
AD
b9
2
10-bit Result
T
ADRESL
AD
b8
3
T
AD
b7
AD
4
0
CYCLES
T
AD
b6
10-bit Result
5
T
AD
b5
6
acquisition is started. After this 2 T
on the selected channel is automatically started. The
GO/DONE bit can then be set to start the conversion.
In Figure 10-3, after the GO bit is set, the first time
segment has a minimum of T
mat Select bit (ADFM) controls this justification.
Figure 10-4 shows the operation of the A/D result justifi-
cation. The extra bits are loaded with ‘0’. When an A/D
result will not overwrite these locations (A/D disable),
these registers may be used as two general purpose
8-bit registers.
T
ADRES is loaded
GO bit is cleared
ADIF bit is set
Holding capacitor is connected to analog input
AD
b4
Note:
7
7
T
AD
b3
ADRESH
8
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
10-bit Result
T
AD
b2
ADFM = 0
9
Left Justified
T
0 7 6 5
AD
b1
10 T
2003 Microchip Technology Inc.
ADRESL
CY
AD
b0
0000 00
11
and a maximum of T
AD
0
wait, acquisition
AD
.
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