PIC18C801-I/L Microchip Technology, PIC18C801-I/L Datasheet - Page 2

• Manufacturer Part Number: PIC18C801-I/L
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,84PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C801-I/L

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Type: ROMless
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: 3-Wire, I2C, SPI, USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 47
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCXLT84L1 - SOCKET TRANSITION ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C801-I/LR; PIC18C801-I/LR; PIC18C801I/L

PIC18C601/801
Clarifications/Corrections to the Data Sheet:
In the Device Data Sheet (DS39541A), the following
clarifications and corrections should be noted.
1. Module: Core (DC Characteristics)
2. Module: Interrupts
REGISTER 8-1:
FIGURE 1:
DS80108B-page 2
The specification for the device Supply Current
(parameter D013, F
has changed. The new maximum value is 65 mA.
This new value applies to both standard and
extended voltage range devices.
The operation of the GIE/GIEH bit (INTCON<7>) is
clarified as follows: when the bit is cleared, all
interrupts are disabled. This is regardless of the
state of the IPEN bit (RCON<7>), the priority of the
interrupt, or whether or not the interrupt is
Low Priority Interrupt Generation
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit
Peripheral Interrupt Flag bit
bit 7
TMR1IE
TMR1IP
TMR1IF
XXXXIE
XXXXIP
XXXXIF
INTERRUPT LOGIC (EXCERPT)
INTCON REGISTER (EXCERPT)
GIE/GIEH: Global Interrupt Enable bit
When IPEN (RCON<7>) = 0:
1 = Enables all unmasked interrupts
0 = Disables all interrupts
When IPEN (RCON<7>) = 1:
1 = Enables all high priority interrupts
0 = Disables all interrupts
OSC
= 25 MHz, V
Additional Peripheral Interrupts
DD
= 5.5V)
TMR0IF
TMR0IE
TMR0IP
INT1IE
INT1IP
INT2IE
INT2IP
INT1IF
INT2IF
RBIE
RBIF
RBIP
unmasked. This varies from the original descrip-
tion, in which clearing the bit when IPEN = ’1’
would only disable high priority interrupts.
The seventh paragraph in Section 8.0 of the
Device Data Sheet (beginning “When an interrupt
is responded to....”) is amended by adding the fol-
lowing sentence to the end:
“It is important to note, however, that clearing the
GIE/GIEH bit, regardless of the state of the IPEN
bit, will disable all interrupts.”
The changes to the bit descriptions in Register 8-1
in the Device Data Sheet are shown in the excerpt
below (changes in bold).
Also, the interrupt logic funnel shown in Figure 1 of
the Device Data Sheet is amended with the addi-
tion of a GIE/GIEH control line, as shown in
Figure 1 (new material in bold line).
 2002 Microchip Technology Inc.
GIEL/PEIE
GIE/GEIH
Interrupt to CPU
Vector to Location
0018h