PIC18F25J10T-I/SS Microchip Technology, PIC18F25J10T-I/SS Datasheet - Page 16

• Manufacturer Part Number: PIC18F25J10T-I/SS
• Description: Microcontroller
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F25J10T-I/SS

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPIC, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DM183032, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• A/d Bit Size: 10 bit
• A/d Channels Available: 10
• Height: 1.75 mm
• Length: 10.2 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.2 V
• Width: 5.3 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180011 - MODULE PLUG-IN 18F25J10 28SOICAC162067 - HEADER INTRFC MPLAB ICD2 40/28PAC164331 - MODULE SKT FOR 28SSOP 18F45J10
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18F25J10T-I/SSTR

PIC18F2XJXX/4XJXX FAMILY
4.0
4.1
Code memory is accessed one byte at a time via the
4-bit command, ‘1001’ (table read, post-increment).
The contents of memory pointed to by the Table Pointer
(TBLPTRU:TBLPTRH:TBLPTRL) are serially output on
PGD.
The 4-bit command is shifted in LSb first. The read is
executed during the next 8 clocks, then shifted out on
PGD during the last 8 clocks, LSb to MSb. A delay of
TABLE 4-1:
FIGURE 4-1:
DS39687E-page 16
Step 1: Set Table Pointer.
Step 2: Read memory and then shift out on PGD, LSb to MSb.
Command
PGC
PGD
0000
0000
0000
0000
0000
0000
1001
4-Bit
READING THE DEVICE
Read Code Memory
1
1
2
0E <Addr[21:16]>
6E F8
0E <Addr[15:8]>
6E F7
0E <Addr[7:0]>
6E F6
00 00
0
READ CODE MEMORY SEQUENCE
3
0
Data Payload
TABLE READ, POST-INCREMENT INSTRUCTION TIMING (1001)
4
1
P5
PGD = Input
1
2
3
MOVLW Addr[21:16]
MOVWF TBLPTRU
MOVLW <Addr[15:8]>
MOVWF TBLPTRH
MOVLW <Addr[7:0]>
MOVWF TBLPTRL
TBLRD *+
4
5
6
7
8
P6
P6 must be introduced after the falling edge of the 8th
PGC of the operand to allow PGD to transition from an
input to an output. During this time, PGC must be held
low (see Figure 4-1). This operation also increments
the Table Pointer by one, pointing to the next byte in
code memory for the next read.
This technique will work to read any memory in the
000000h to 3FFFFFh address space, so it also applies
to reading the Configuration registers.
9
LSb
P14
10
1
11
Core Instruction
2
PGD = Output
12
Shift Data Out
3
13
4
14
5
15
6
© 2009 Microchip Technology Inc.
16
MSb
P5A
Fetch Next 4-Bit Command
1
PGD = Input
n
2
n
3
n
4
n