PIC18F4420T-I/PT Microchip Technology, PIC18F4420T-I/PT Datasheet - Page 114
PIC18F4420T-I/PT
Manufacturer Part Number
PIC18F4420T-I/PT
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,44PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(46 pages)
2.PIC18F2420-IML.pdf
(412 pages)
3.PIC18F2420-IML.pdf
(16 pages)
4.PIC18F2420-IML.pdf
(8 pages)
5.PIC18F2420-IML.pdf
(6 pages)
6.PIC18F2420-IML.pdf
(8 pages)
7.PIC18F2420-IML.pdf
(4 pages)
Specifications of PIC18F4420T-I/PT
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F4420T-I/PT
Manufacturer:
MICROCHIP
Quantity:
4 000
Company:
Part Number:
PIC18F4420T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC18F2221-ISO PDF datasheet
- PIC18F2420-IML PDF datasheet #2
- PIC18F2420-IML PDF datasheet #3
- PIC18F2420-IML PDF datasheet #4
- PIC18F2420-IML PDF datasheet #5
- PIC18F2420-IML PDF datasheet #6
- PIC18F2420-IML PDF datasheet #7
- Current page: 114 of 412
- Download datasheet (7Mb)
PIC18F2420/2520/4420/4520
TABLE 10-5:
DS39631E-page 112
RC0/T1OSO/
T13CKI
RC1/T1OSI/CCP2
RC2/CCP1/P1A
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
Legend:
Note 1:
2:
Pin
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
I
Default assignment for CCP2 when the CCP2MX Configuration bit is set. Alternate assignment is RB3.
Enhanced PWM output is available only on PIC18F4520 devices.
2
C/SMB = I
PORTC I/O SUMMARY
Function
CCP2
T1OSO
T13CKI
T1OSI
P1A
CCP1
SDO
RC0
RC1
RC2
RC3
SCK
RC4
SDA
RC5
RC6
RC7
SCL
SDI
CK
RX
TX
DT
2
C/SMBus input buffer; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
(2)
(1)
Setting
TRIS
0
1
x
1
0
1
x
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
1
1
1
0
1
0
0
1
1
1
1
0
1
1
1
1
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
2
2
C/SMB I
C/SMB I
Type
ANA
ANA
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
LATC<0> data output.
PORTC<0> data input.
Timer1 oscillator output; enabled when Timer1 oscillator enabled.
Disables digital I/O.
Timer1/Timer3 counter input.
LATC<1> data output.
PORTC<1> data input.
Timer1 oscillator input; enabled when Timer1 oscillator enabled.
Disables digital I/O.
CCP2 compare and PWM output; takes priority over port data.
CCP2 capture input.
LATC<2> data output.
PORTC<2> data input.
ECCP1 compare or PWM output; takes priority over port data.
ECCP1 capture input.
ECCP1 Enhanced PWM output, channel A. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data.
LATC<3> data output.
PORTC<3> data input.
SPI clock output (MSSP module); takes priority over port data.
SPI clock input (MSSP module).
I
LATC<4> data output.
PORTC<4> data input.
SPI data input (MSSP module).
I
LATC<5> data output.
PORTC<5> data input.
SPI data output (MSSP module); takes priority over port data.
LATC<6> data output.
PORTC<6> data input.
Asynchronous serial transmit data output (EUSART module);
takes priority over port data. User must configure as output.
Synchronous serial clock output (EUSART module); takes priority
over port data.
Synchronous serial clock input (EUSART module).
LATC<7> data output.
PORTC<7> data input.
Asynchronous serial receive data input (EUSART module).
Synchronous serial data output (EUSART module); takes priority over
port data.
Synchronous serial data input (EUSART module). User must
configure as an input.
2
2
2
2
C™ clock output (MSSP module); takes priority over port data.
C clock input (MSSP module); input type depends on module setting.
C data output (MSSP module); takes priority over port data.
C data input (MSSP module); input type depends on module setting.
Description
© 2008 Microchip Technology Inc.
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