PIC18F64J90-I/PT Microchip Technology, PIC18F64J90-I/PT Datasheet - Page 2

• Manufacturer Part Number: PIC18F64J90-I/PT
• Description: Microcontroller
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F64J90-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F85J90 FAMILY
4. Module: MSSP (I
5. Module: MSSP (I
DS80472A-page 2
In extremely rare cases, when configured for I
slave reception, the MSSP module may not receive
the correct data. This occurs only if the Serial
Receive/Transmit Buffer Register (SSPBUF) is not
read within a window after the SSPIF interrupt
(PIR1<3>) has occurred.
Work around
The issue can be resolved either of these ways:
• Prior to the I
• Each time the SSPIF is set, read the SSPBUF
Date Codes that pertain to this issue:
All engineering and production devices.
When in I
clock stretching, the first clock pulse after the slave
releases the SCL line may be narrower than the
configured clock width. This may result in the slave
missing the first clock in the next transmission/
reception.
Work around
The clock pulse will be the normal width if the slave
does not perform clock stretching.
Date Codes that pertain to this issue:
All engineering and production devices
clock stretching feature.
This
(SSPCON2<0>).
before the first rising clock edge of the next byte
being received.
is
2
C Master mode, if the slave performs
done
2
C slave reception, enable the
2
2
by
C™ Slave)
C™ Master)
setting
the
SEN
2
C™
bit
6. Module: Enhanced Universal
1.
2.
3.
4.
5.
In rare situations, when interrupts are enabled,
unexpected results may occur if:
• The EUSART is disabled (the SPEN bit,
• The EUSART is re-enabled (RCSTA<7> = 1)
• A two-cycle instruction is executed
Work around
Add a 2 T
Disable
PIE1<5> = 0).
Disable the EUSART (RCSTA<7> = 0).
Re-enable the EUSART (RCSTA<7> = 1).
Re-enable receive interrupts (PIE1<5> = 1).
(This is the first T
Execute a NOP instruction.
(This is the second T
Date Codes that pertain to this issue:
All engineering and production devices.
RCSTA<7> = 0)
CY
Synchronous Asynchronous
Receiver Transmitter (EUSART)
receive
delay after re-enabling the EUSART.
CY
© 2009 Microchip Technology Inc.
delay.)
CY
interrupts
delay.)
(RCIE
bit,