PIC18F64J90-I/PT Microchip Technology, PIC18F64J90-I/PT Datasheet - Page 4
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PIC18F64J90-I/PT
Manufacturer Part Number
PIC18F64J90-I/PT
Description
Microcontroller
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F63J11-IPT.pdf
(36 pages)
3.PIC18F63J90-IPT.pdf
(416 pages)
4.PIC18F63J90-IPT.pdf
(22 pages)
5.PIC18F63J90-IPT.pdf
(4 pages)
6.PIC18F63J90-IPT.pdf
(6 pages)
7.PIC18F63J90-IPT.pdf
(6 pages)
8.PIC18F63J90-IPT.pdf
(12 pages)
Specifications of PIC18F64J90-I/PT
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
Number Of I /o
51
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F64J90-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC18F85J90 FAMILY
5. Module: Timer 1/3
6. Module: Timer 1/3
DS80488B-page 4
When either Timer1 or Timer3 is configured for
the
TxCON<1>(TMRxCS) = 0) and in the 8/16-Bit
Counter mode (TxCON<7>(RD16) = 0 or 1),
TMRxH and TMRxL will not increment on the
instruction that turns off the counter (TxCON<0>
(TMRxON) = 0).
Work around
None.
Affected Silicon Revisions
When either Timer1 or Timer3 is in the 8/16-Bit
Counter mode (TXCON<7> (RD16) = 0 or 1),
incrementing the prescale value (TxCON<5:4>
(TXCKPS<1:0>)) will take an additional count at
the previous value before the prescale value is
updated.
For example, changing the prescale value from
1:4 to 1:8 will occur four instruction cycles after
the execution of the instruction to update the
prescaler.
Work around
None.
Affected Silicon Revisions
A3
A3
X
X
internal
A4
A4
X
X
A5
A5
X
X
clock
A6
A6
X
X
source
(F
OSC
/4,
7. Module: Enhanced Universal
In Synchronous Slave Transmission mode, the
TRMT bit (TXSTA<1> may not indicate when the
TSR register is empty.
Work around
Instead of polling the TRMT bit to determine the
status of the EUSART, poll the TXIF flag
(PIR1<4>) to determine when new data can be
written to the TXREG register.
Affected Silicon Revisions
A3
X
A4
X
Synchronous Asynchronous
Receiver Transmitter (EUSART)
A5
X
2010 Microchip Technology Inc.
A6
X