PIC18F66J65T-I/PT Microchip Technology, PIC18F66J65T-I/PT Datasheet - Page 326
![96KB Flash, 12KB RAM, 10BASE-T Ethernet 64 TQFP 10x10x1mm T/R](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F66J65T-I/PT
Manufacturer Part Number
PIC18F66J65T-I/PT
Description
96KB Flash, 12KB RAM, 10BASE-T Ethernet 64 TQFP 10x10x1mm T/R
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F63J11-IPT.pdf
(36 pages)
3.PIC18F66J65-IPT.pdf
(8 pages)
4.PIC18F66J65-IPT.pdf
(480 pages)
5.PIC18F66J65-IPT.pdf
(4 pages)
6.PIC18F66J65-IPT.pdf
(10 pages)
Specifications of PIC18F66J65T-I/PT
Core Processor
PIC
Core Size
8-Bit
Speed
41.667MHz
Connectivity
Ethernet, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
96KB (48K x 16)
Program Memory Type
FLASH
Ram Size
3808 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3808 B
Interface Type
Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
41.667 MHz
Number Of Programmable I/os
39
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162064 - HEADER INTFC MPLABICD2 64/80/100AC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F66J65T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18F63J11-IPT PDF datasheet #2
- PIC18F66J65-IPT PDF datasheet #3
- PIC18F66J65-IPT PDF datasheet #4
- PIC18F66J65-IPT PDF datasheet #5
- PIC18F66J65-IPT PDF datasheet #6
- Current page: 326 of 480
- Download datasheet (8Mb)
Synchronous Master mode in that the shift clock is sup-
PIC18F97J60 FAMILY
TABLE 20-8:
20.4
Synchronous Slave mode is entered by clearing bit,
CSRC (TXSTAx<7>). This mode differs from the
plied externally at the CKx pin (instead of being supplied
internally in Master mode). This allows the device to
transfer or receive data while in any low-power mode.
20.4.1
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep mode.
If two words are written to the TXREGx and then the
SLEEP instruction is executed, the following will occur:
a)
b)
c)
d)
e)
DS39762E-page 326
INTCON
PIR1
PIE1
IPR1
PIR3
PIE3
IPR3
RCSTAx
RCREGx
TXSTAx
BAUDCONx ABDOVF
SPBRGHx EUSARTx Baud Rate Generator Register High Byte
SPBRGx
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
Note 1:
Name
The first word will immediately transfer to the
TSR register and transmit.
The second word will remain in the TXREGx
register.
Flag bit, TXxIF, will not be set.
When the first word has been shifted out of TSR,
the TXREGx register will transfer the second word
to the TSR and flag bit, TXxIF, will now be set.
If enable bit, TXxIE, is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
EUSARTx Synchronous
Slave Mode
These bits are only available in 80-pin and 100-pin devices; otherwise, they are unimplemented and read as ‘0’.
EUSARTx SYNCHRONOUS
SLAVE TRANSMISSION
EUSARTx Receive Register
EUSARTx Baud Rate Generator Register Low Byte
GIE/GIEH PEIE/GIEL TMR0IE
SSP2IE
SSP2IP
SSP2IF
PSPIF
PSPIE
PSPIP
CSRC
SPEN
Bit 7
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
BCL2IF
BCL2IE
BCL2IP
RCIDL
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
RC2IE
RC2IP
RC2IF
RXDTP
RC1IF
RC1IE
RC1IP
SREN
TXEN
Bit 5
(1)
(1)
(1)
TXCKP
INT0IE
CREN
TX1IF
TX1IE
TX1IP
TX2IF
TX2IE
TX2IP
SYNC
Bit 4
TMR4IF
TMR4IE
TMR4IP
SSP1IE
SSP1IP
ADDEN
SSP1IF
SENDB
BRG16
To set up a Synchronous Slave Transmission:
1.
2.
3.
4.
5.
6.
7.
8.
9.
RBIE
Bit 3
Enable the synchronous slave serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
Clear bits, CREN and SREN.
If the signal from the CKx pin is to be inverted,
set the TXCKP bit. If the signal from the DTx pin
is to be inverted, set the RXDTP bit.
If interrupts are desired, set enable bit, TXxIE.
If 9-bit transmission is desired, set bit, TX9.
Enable the transmission by setting enable bit,
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the
TXREGx register.
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TMR0IF
CCP1IE
CCP1IP
CCP5IE
CCP5IP
CCP1IF
CCP5IF
BRGH
FERR
Bit 2
—
TMR2IF
TMR2IE
TMR2IP
CCP4IE
CCP4IP
CCP4IF
INT0IF
OERR
TRMT
© 2009 Microchip Technology Inc.
WUE
Bit 1
TMR1IF
TMR1IE
TMR1IP
CCP3IE
CCP3IP
CCP3IF
ABDEN
RX9D
TX9D
RBIF
Bit 0
on Page:
Values
Reset
63
65
65
65
65
65
65
65
65
65
66
66
66
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