PIC18F67J60T-I/PT Microchip Technology, PIC18F67J60T-I/PT Datasheet - Page 45
![128KB Flash, 12KB RAM, 10BASE-T Ethernet 64 TQFP 10x10x1mm T/R](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F67J60T-I/PT
Manufacturer Part Number
PIC18F67J60T-I/PT
Description
128KB Flash, 12KB RAM, 10BASE-T Ethernet 64 TQFP 10x10x1mm T/R
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F66J65-IPT.pdf
(8 pages)
2.PIC18F66J65-IPT.pdf
(480 pages)
3.PIC18F66J65-IPT.pdf
(4 pages)
4.PIC18F66J65-IPT.pdf
(10 pages)
Specifications of PIC18F67J60T-I/PT
Core Processor
PIC
Core Size
8-Bit
Speed
41.667MHz
Connectivity
Ethernet, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Ram Size
3808 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3808 B
Interface Type
Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
41.667 MHz
Number Of Programmable I/os
39
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM183033 - BOARD DEMO INTERNET RADIOAC162064 - HEADER INTFC MPLABICD2 64/80/100AC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F67J60T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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2.5
The PIC18F97J60 family of devices includes an internal
oscillator source (INTRC) which provides a nominal
31 kHz output. The INTRC is enabled on device
power-up and clocks the device during its configuration
cycle until it enters operating mode. INTRC is also
enabled if it is selected as the device clock source or if
any of the following are enabled:
• Fail-Safe Clock Monitor
• Watchdog Timer
• Two-Speed Start-up
These features are discussed in greater detail in
Section 24.0 “Special Features of the CPU”.
The INTRC can also be optionally configured as the
default clock source on device start-up by setting the
FOSC2 Configuration bit. This is discussed in
Section 2.7.1 “Oscillator Control Register”.
2.6
Although devices of the PIC18F97J60 family can accept
a wide range of crystals and external oscillator inputs,
they must always have a 25 MHz clock source when
REGISTER 2-1:
© 2009 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3-0
Note 1:
PPST1
R/W-0
Internal Oscillator Block
Ethernet Operation and the
Microcontroller Clock
Available only for ECPLL and HSPLL oscillator configurations; otherwise, this bit is unavailable and is read
as ‘0’.
PPST1: PLL Postscaler Configuration bit
1 = Divide-by-2
0 = Divide-by-3
PLLEN: 5x Frequency Multiplier PLL Enable bit
1 = PLL enabled
0 = PLL disabled
PPST0: PLL Postscaler Enable bit
1 = Postscaler enabled
0 = Postscaler disabled
PPRE: PLL Prescaler Configuration bit
1 = Divide-by-2
0 = Divide-by-3
Unimplemented: Read as ‘0’
PLLEN
R/W-0
OSCTUNE: PLL BLOCK CONTROL REGISTER
(1)
W = Writable bit
‘1’ = Bit is set
PPST0
R/W-0
R/W-0
PPRE
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PIC18F97J60 FAMILY
used for Ethernet applications. No provision is made for
internally generating the required Ethernet clock from a
primary oscillator source of a different frequency. A
frequency tolerance is specified, likely excluding the use
of ceramic resonators. See Section 27.0 “Electrical
Characteristics”, Table 27-6, parameter 5, for more
details.
2.6.1
To accommodate a range of applications and micro-
controller clock speeds, a separate PLL block is
incorporated into the clock system. It consists of three
components:
• A configurable prescaler (1:2 or 1:3)
• A 5x PLL frequency multiplier
• A configurable postscaler (1:1, 1:2, or 1:3)
The operation of the PLL block’s components is
controlled by the OSCTUNE register (Register 2-1).
The use of the PLL block’s prescaler and postscaler,
with or without the PLL itself, provides a range of sys-
tem clock frequencies to choose from, including the
unaltered 25 MHz of the primary oscillator. The full
range of possible oscillator configurations compatible
with Ethernet operation is shown in Table 2-2.
U-0
(1)
—
PLL BLOCK
U-0
—
x = Bit is unknown
U-0
—
DS39762E-page 45
U-0
—
bit 0
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