PIC18F86J11T-I/PT Microchip Technology, PIC18F86J11T-I/PT Datasheet - Page 28
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PIC18F86J11T-I/PT
Manufacturer Part Number
PIC18F86J11T-I/PT
Description
64KB Flash, 3936 Bytes RAM, 10 MIPS, 67 I/O, NanoWatt 80 TQFP 12x12x1mm T/R
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.DV164136.pdf
(448 pages)
3.PIC18F63J11-IPT.pdf
(36 pages)
4.PIC18F66J11-IPT.pdf
(20 pages)
Specifications of PIC18F86J11T-I/PT
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Ram Size
3930 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 15x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TFQFP
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3904 B
Interface Type
EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
68
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183022, DM183032
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 15 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162091 - HEADER MPLAB ICD2 18F87J11 64/80MA180020 - MODULE PLUG-IN HPC EXPL 18F87J11AC164328 - MODULE SKT FOR 80TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
PIC18F86J11T-I/PTTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F86J11T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC18F6XJXX/8XJXX
5.2
The checksum is calculated by summing the following:
• The contents of all code memory locations
• The Configuration Block (CFGB), appropriately
• ID locations
The Least Significant 16 bits of this sum are the
checksum.
Table 5-5 (pages 28 through 30) describes how to
calculate the checksum for each device.
TABLE 5-5:
DS39644L-page 28
CFGB80 = Byte sum of [(CW1 & 0CE1h) + (CW2 & 0FC7h) + (CW3 & 01F8h)]
CFGB60 = Byte sum of [(CW1 & 0CE1h) + (CW2 & 0FC7h) + (CW3 & 0100h)]
Legend: Item
masked
Note:
PIC18F85J11
Family
Checksum Computation
SUM(a:b) =
+
CW
CFGB
CW3 address is the last location – 2 of implemented program memory; CW2 is the last location – 4;
CW1 is the last location – 6.
CHECKSUM EQUATION FOR PIC18F6XJXX/8XJXX
=
=
=
PIC18F63J11
PIC18F64J11
PIC18F64J16
PIC18F65J11
PIC18F83J11
PIC18F84J11
PIC18F84J16
PIC18F85J11
Description
Byte sum of locations a to b inclusive (all 3 bytes of code memory)
Addition
Configuration Word
Configuration Block (Masked)
Device
Read Code Protection
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Note:
The checksum calculation differs depend-
ing on the code-protect setting. Since the
code memory locations read out differently
depending on the code-protect setting, the
table describes how to manipulate the
actual code memory values to simulate the
values that would be read from a protected
device. When calculating a checksum by
reading a device, the entire code memory
can simply be read and summed. The
Configuration Word and ID locations can
always be read.
CFGB60 + SUM(0000:1FF7h)
CFGB60 + SUM(0000:3FF7h)
CFGB60 + SUM(0000:5FF7h)
CFGB60 + SUM(0000:7FF7h)
CFGB80 + SUM(0000:1FF7h)
CFGB80 + SUM(0000:3FF7h)
CFGB80 + SUM(0000:5FF7h)
CFGB80 + SUM(0000:7FF7h)
Checksum Computation
2009 Microchip Technology Inc.
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h