PIC18LF2221-I/ML Microchip Technology, PIC18LF2221-I/ML Datasheet - Page 121
![4 KB Flash, 512 RAM 28 QFN 6x6mm TUBE](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC18LF2221-I/ML
Manufacturer Part Number
PIC18LF2221-I/ML
Description
4 KB Flash, 512 RAM 28 QFN 6x6mm TUBE
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(402 pages)
2.PIC18F2221-ISO.pdf
(8 pages)
3.PIC18F2221-ISO.pdf
(30 pages)
4.PIC18F2221-ISO.pdf
(46 pages)
5.PIC18LF2221-IML.pdf
(394 pages)
Specifications of PIC18LF2221-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF2221-I/ML
Manufacturer:
Microchip Technology
Quantity:
135
Part Number:
PIC18LF2221-I/ML
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC18F2221-ISO PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F2221-ISO PDF datasheet #3
- PIC18F2221-ISO PDF datasheet #4
- PIC18LF2221-IML PDF datasheet #5
- Current page: 121 of 402
- Download datasheet (7Mb)
TABLE 11-7:
© 2009 Microchip Technology Inc.
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
Legend:
Pin
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; x = Don’t care
(TRIS bit does not affect port direction or is overridden for this option).
PORTD I/O SUMMARY
Function
PSP0
PSP1
PSP2
PSP3
PSP4
PSP5
PSP6
PSP7
RD0
RD1
RD2
RD3
RD4
RD5
P1B
RD6
P1C
RD7
P1D
PIC18F2221/2321/4221/4321 FAMILY
Setting
TRIS
0
1
x
x
0
1
x
x
0
1
x
x
0
1
x
x
0
1
x
x
0
1
x
x
0
0
1
x
x
0
0
1
x
x
0
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Type
DIG
DIG
TTL
DIG
DIG
TTL
DIG
DIG
TTL
DIG
DIG
TTL
DIG
DIG
TTL
DIG
DIG
TTL
DIG
DIG
DIG
TTL
DIG
DIG
DIG
TTL
DIG
I/O
ST
ST
ST
ST
ST
ST
ST
ST
LATD<0> data output.
PORTD<0> data input.
PSP read data output (LATD<0>); takes priority over port data.
PSP write data input.
LATD<1> data output.
PORTD<1> data input.
PSP read data output (LATD<1>); takes priority over port data.
PSP write data input.
LATD<2> data output.
PORTD<2> data input.
PSP read data output (LATD<2>); takes priority over port data.
PSP write data input.
LATD<3> data output.
PORTD<3> data input.
PSP read data output (LATD<3>); takes priority over port data.
PSP write data input.
LATD<4> data output.
PORTD<4> data input.
PSP read data output (LATD<4>); takes priority over port data.
PSP write data input.
LATD<5> data output.
PORTD<5> data input.
PSP read data output (LATD<5>); takes priority over port data.
PSP write data input.
ECCP1 Enhanced PWM output, Channel B; takes priority over port and
PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
LATD<6> data output.
PORTD<6> data input.
PSP read data output (LATD<6>); takes priority over port data.
PSP write data input.
ECCP1 Enhanced PWM output, channel C; takes priority over port and
PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
LATD<7> data output.
PORTD<7> data input.
PSP read data output (LATD<7>); takes priority over port data.
PSP write data input.
ECCP1 Enhanced PWM output, Channel D; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
Description
DS39689F-page 121
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