PIC18LF2420T-I/ML Microchip Technology, PIC18LF2420T-I/ML Datasheet - Page 12
![28 PIN, 16 KB ENHFLASH, 768 B RAM, 25 I/O PB FREE,](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC18LF2420T-I/ML
Manufacturer Part Number
PIC18LF2420T-I/ML
Description
28 PIN, 16 KB ENHFLASH, 768 B RAM, 25 I/O PB FREE,
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2420-IML.pdf
(412 pages)
2.PIC18F2420-IML.pdf
(16 pages)
3.PIC18F2420-IML.pdf
(8 pages)
4.PIC18F2420-IML.pdf
(6 pages)
5.PIC18F2420-IML.pdf
(8 pages)
6.PIC18F2420-IML.pdf
(4 pages)
Specifications of PIC18LF2420T-I/ML
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF2420T-I/ML
Manufacturer:
MICROCHIP
Quantity:
1 001
PIC18F2420/2520/4420/4520
39. Module: MSSP
40. Module: MSSP
EXAMPLE 5:
41. Module: Timer1
DS80209H-page 12
In SPI mode, the SDO output may change after the
inactive clock edge of the bit ‘0’ output. This may
affect some SPI components that read data over
300 ns after the inactive edge of SCK.
Work around
None
Date Codes that pertain to this issue:
All engineering and production devices.
When the MSSP is configured for SPI mode, the
Buffer Full bit, BF (SSPSTAT<0>), should not be
polled in software to determine when the transfer
is complete.
Work around
Copy the SSPSTAT register into a variable and
perform the bit test on the variable. In Example 5,
SSPSTAT is copied into the working register
where the bit test is performed.
A second option is to poll the Master Synchronous
Serial Port Interrupt Flag bit, SSPIF (PIR1<3>).
This bit can be polled and will set when the transfer
is complete.
Date Codes that pertain to this issue:
All engineering and production devices.
In 16-Bit Asynchronous Counter mode (with or
without use of the Timer1 oscillator), the TMR1H
and TMR3H buffers do not update when TMRxL is
read.
This issue only affects reading the TMRxH regis-
ters. The timers increment and set the interrupt
flags as expected. The timer registers can also be
written as expected.
Work around
1. Use 8-bit mode by clearing the RD16 bit
2. Use the internal clock synchronization option
Date Codes that pertain to this issue:
All engineering and production devices.
loop_MSB:
(T1CON<7>).
by clearing the T1SYNC bit (T1CON<2>).
MOVF
BTFSS
BRA
SSPSTAT, W
WREG, BF
loop_MSB
42. Module: Reset
43. Module: 10-Bit Analog-to-Digital
This version of silicon does not support the func-
tionality described in Note 1 of parameter D002 in
Section 26.1 “DC Characteristics: Supply
Voltage” of the data sheet. The RAM content may
be altered during a Reset event if the following
conditions are met.
• Device is accessing RAM.
• Asynchronous Reset (i.e., WDT, BOR or
Work around
None
Date Codes that pertain to this issue:
All engineering and production devices.
When the AD clock source is selected as 2 T
RC (when ADCS2:ADCS0 = 000 or x11), in
extremely rare cases, the E
Error) and E
exceed the data sheet specification at codes 511
and 512 only.
Work around
Select the AD clock source as 4 T
16 T
2 T
Date Codes that pertain to this issue:
All engineering and production devices.
MCLR) occurs when a write operation is being
executed (start of a Q4 cycle).
OSC
OSC
or RC.
, 32 T
Converter
DL
OSC
(Differential Linearity Error) may
or 64 T
© 2008 Microchip Technology Inc.
OSC
IL
and avoid selecting
(Integral Linearity
OSC
, 8 T
OSC
OSC
or
,