PIC18LF24J10-I/ML Microchip Technology, PIC18LF24J10-I/ML Datasheet - Page 4
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PIC18LF24J10-I/ML
Manufacturer Part Number
PIC18LF24J10-I/ML
Description
Microcontroller
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F24J10-ISO.pdf
(368 pages)
3.PIC18F24J10-ISO.pdf
(6 pages)
4.PIC18F24J10-ISO.pdf
(6 pages)
5.PIC18F24J10-ISO.pdf
(12 pages)
6.PIC18LF24J10-ISS.pdf
(32 pages)
Specifications of PIC18LF24J10-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPIC, I2C, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180012 - MODULE PLUG-IN 18LF25J10 28SOICAC162067 - HEADER INTRFC MPLAB ICD2 40/28PXLT28QFN4 - SOCKET TRANS ICE 28QFN W/CABLE
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF24J10-I/ML
Manufacturer:
MICROCHIP
Quantity:
12 000
PIC18F45J10 FAMILY
6. Module: MSSP
7. Module: MSSP (I
DS80494B-page 4
In SPI mode, the Buffer Full flag bit (BF,
SSPxSTAT<0>), the Write Collision Detect bit
(WCOL, SSPxCON1<7>) and the Receive Over-
flow Indicator bit (SSPOV, SSPxCON1<6>) are
not reset upon disabling the SPI module (by
clearing the SSPEN bit in the SSPxCON1
register).
For example, if SSPxBUF is full (BF bit is set)
and the MSSP module is disabled and re-
enabled, the BF bit will remain set. In SPI Slave
mode, a subsequent write to SSPxBUF will
result in a write collision. Also, if a new byte is
received, a receive overflow will occur.
Work around
Ensure that if the buffer is full, SSPxBUF is read
(thus, clearing the BF flag) and WCOL is clear
before disabling the MSSP module. If the
module is configured in SPI Slave mode, ensure
that the SSPOV bit is clear before disabling the
module.
Affected Silicon Revisions
After a Power-on Reset, the I
initialize properly by just configuring the SCLx
and SDAx pins as either inputs or outputs. This
has only been seen in a few unique system
environments.
A test of a statistically significant sample of pre-
production systems, across the voltage and
current range of the application’s power supply,
should indicate if a system is susceptible to this
issue.
Work around
Before configuring the module for I
1. Configure the SCLx and SDAx pins as outputs
2. Force SCLx and SDAx low by clearing the
3. While keeping the LAT bits clear, configure
Once this is done, use the SSPxCON1 and
SSPxCON2 registers to configure the proper
I
Affected Silicon Revisions
2
A2
C mode as before.
A2
X
X
by clearing their corresponding TRIS bits.
corresponding LAT bits.
SCLx and SDAx as inputs by setting their TRIS
bits.
A3
A3
X
X
A4
A4
X
X
2
C™ Mode)
2
C mode may not
2
C operation:
8. Module: Core (Program Memory Space)
1.
2.
Writes to program memory address, 300000h,
that are not blocked, can cause the program
memory at different locations to be corrupted.
Work around
Do not write to address, 300000h.
If you wish to modify the contents of the
Configuration registers:
Modify the Configuration Words located at the
end of the user memory:
• For PIC18FX5J10 devices – 7FF4h
• For PIC18FX4J10 devices – 3FF4h
Issue a Reset command.
This will reload the Configuration registers with
the new configuration setting.
Affected Silicon Revisions
A2
X
A3
X
A4
X
2009 Microchip Technology Inc.