PIC18LF24J10-I/SO Microchip Technology, PIC18LF24J10-I/SO Datasheet - Page 219
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18LF24J10-I/SO
Manufacturer Part Number
PIC18LF24J10-I/SO
Description
Microcontroller
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F24J10-ISO.pdf
(368 pages)
3.PIC18F24J10-ISO.pdf
(6 pages)
4.PIC18F24J10-ISO.pdf
(6 pages)
5.PIC18F24J10-ISO.pdf
(12 pages)
6.PIC18LF24J10-ISS.pdf
(32 pages)
Specifications of PIC18LF24J10-I/SO
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPIC, I2C, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180012 - MODULE PLUG-IN 18LF25J10 28SOICAC162067 - HEADER INTRFC MPLAB ICD2 40/28PAC164332 - MODULE SKT FOR 28SOIC 18F45J10
Eeprom Size
-
Lead Free Status / Rohs Status
Details
- PIC16F616T-ISL PDF datasheet
- PIC18F24J10-ISO PDF datasheet #2
- PIC18F24J10-ISO PDF datasheet #3
- PIC18F24J10-ISO PDF datasheet #4
- PIC18F24J10-ISO PDF datasheet #5
- PIC18LF24J10-ISS PDF datasheet #6
- Current page: 219 of 368
- Download datasheet (6Mb)
REGISTER 18-3:
bit 7
bit 6
bit 5-3
bit 2-0
© 2009 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
Note 1:
R/W-0
ADFM
If the A/D F
clock starts. This allows the SLEEP instruction to be executed before starting a conversion.
ADFM: A/D Result Format Select bit
1 = Right justified
0 = Left justified
Unimplemented: Read as ‘0’
ACQT<2:0>: A/D Acquisition Time Select bits
111 = 20 T
110 = 16 T
101 = 12 T
100 = 8 T
011 = 6 T
010 = 4 T
001 = 2 T
000 = 0 T
ADCS<2:0>: A/D Conversion Clock Select bits
111 = F
110 = F
101 = F
100 = F
011 = F
010 = F
001 = F
000 = F
U-0
—
ADCON2: A/D CONTROL REGISTER 2
RC
RC
OSC
OSC
OSC
RC
OSC
OSC
OSC
AD
AD
AD
AD
AD
clock source is selected, a delay of one T
AD
AD
AD
(clock derived from A/D RC oscillator)
(clock derived from A/D RC oscillator)
/64
/16
/4
/32
/8
/2
(1)
W = Writable bit
‘1’ = Bit is set
ACQT2
R/W-0
ACQT1
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PIC18F45J10 FAMILY
ACQT0
R/W-0
(1)
(1)
CY
(instruction cycle) is added before the A/D
ADCS2
R/W-0
x = Bit is unknown
ADCS1
R/W-0
DS39682E-page 217
ADCS0
R/W-0
bit 0
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