PIC18LF24J10-I/SS Microchip Technology, PIC18LF24J10-I/SS Datasheet - Page 24
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PIC18LF24J10-I/SS
Manufacturer Part Number
PIC18LF24J10-I/SS
Description
Microcontroller
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F24J10-ISO.pdf
(368 pages)
3.PIC18F24J10-ISO.pdf
(6 pages)
4.PIC18F24J10-ISO.pdf
(6 pages)
5.PIC18F24J10-ISO.pdf
(12 pages)
6.PIC18LF24J10-ISS.pdf
(32 pages)
Specifications of PIC18LF24J10-I/SS
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPIC, I2C, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180012 - MODULE PLUG-IN 18LF25J10 28SOICAC162067 - HEADER INTRFC MPLAB ICD2 40/28PAC164331 - MODULE SKT FOR 28SSOP 18F45J10XLT28SS-1 - SOCKET TRANSITION ICE 28SSOP
Eeprom Size
-
Lead Free Status / Rohs Status
Details
PIC18F2XJXX/4XJXX FAMILY
TABLE 5-7:
DS39687E-page 24
DEBUG
XINST
STVREN
CFGPLLEN
PLLDIV<2:0>
WDTEN
CP0
CPDIV<1:0>
IESO
FCMEN
CLKOEC
SOSCSEL<1:0>
Note 1: The Configuration bits can only be programmed indirectly by programming the Flash Configuration Word.
(4)
Bit Name
2: The Configuration bits are reset to ‘1’ only on V
3: These bits are not implemented in PIC18F47J13 family devices.
4: Once this bit is cleared, all the Configuration registers which reside in the last page are also protected. To disable code
5: Not implemented on PIC18F47J53 family devices.
(3)
protection, perform an ICSP™ Bulk Erase operation.
PIC18F47J13 AND PIC18F47J53 FAMILY DEVICES: BIT DESCRIPTIONS
CONFIG2L
CONFIG2L
Configuration
CONFIG1H
CONFIG1H
CONFIG1L
CONFIG1L
CONFIG1L
CONFIG1L
CONFIG1L
CONFIG1L
CONFIG2L
CONFIG2L
Words
(1,2)
(1,2)
Background Debugger Enable bit
1 = Background debugger disabled, RB6 and RB7 configured as general purpose
0 = Background debugger enabled, RB6 and RB7 are dedicated to in-circuit debug
Enhanced Instruction Set Enable bit
1 = Instruction set extension and Indexed Addressing mode enabled
0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
Stack Overflow/Underflow Reset Enable bit
1 = Reset on stack overflow/underflow enabled
0 = Reset on stack overflow/underflow disabled
Enable PLL on Start-up bit
1 = PLL enabled on start-up. Not recommended for low-voltage designs.
0 = PLL disabled on start-up. Firmware may later enable PLL through OSCTUNE<6>.
96 MHz PLL Input Divider bits
Divider must be selected to provide a 4 MHz input into the 96 MHz PLL.
111 = No divide – oscillator used directly (4 MHz input)
110 = Oscillator divided by 2 (8 MHz input)
101 = Oscillator divided by 3 (12 MHz input)
100 = Oscillator divided by 4 (16 MHz input)
011 = Oscillator divided by 5 (20 MHz input)
010 = Oscillator divided by 6 (24 MHz input)
001 = Oscillator divided by 10 (40 MHz input)
000 = Oscillator divided by 12 (48 MHz input)
Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled (control is placed on SWDTEN bit)
Code Protection bit
1 = Program memory is not code-protected
0 = Program memory is code-protected
CPU System Clock Selection bits
11 = No CPU system clock divide
10 = CPU system clock divided by 2
01 = CPU system clock divided by 3
00 = CPU system clock divided by 6
Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit
1 = Oscillator Switchover mode enabled
0 = Oscillator Switchover mode disabled
Fail-Safe Clock Monitor Enable bit
1 = Fail-Safe Clock Monitor enabled
0 = Fail-Safe Clock Monitor disabled
EC Mode Clock Output Enable bit
1 = CLKO output signal active on the RA6 pin (EC mode only)
0 = CLKO output disabled
Secondary Oscillator Circuit Selection bits
11 = High-power SOSC circuit selected
10 = Digital Input mode (SCLKI)
01 = Low-power SOSC circuit selected
00 = Reserved
I/O pins
DD
Reset; it is reloaded with the programmed value at any device Reset.
Description
© 2009 Microchip Technology Inc.