PIC18LF2685-I/SO Microchip Technology, PIC18LF2685-I/SO Datasheet - Page 2

• Manufacturer Part Number: PIC18LF2685-I/SO
• Description: 96KB Flash, 3KB RAM, ECAN, 1024 EEPROM 28 SOIC .300in TUBE
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF2685-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 96KB (48K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.25 KB
• Interface Type: EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F2682/2685/4682/4685
2. Module: ECAN™ Technology
EXAMPLE 1:
3. Module: Timer1 and Timer3
DS80284E-page 2
If (RXBnOVFL == 1)
Under specific conditions, the TXBxSIDH register
of the pending message for transmission may be
corrupted. The following conditions must exist for
this event to occur:
1. A transmit message must be pending.
2. All of the receive buffers must be full and a
3. A receiver buffer must be made available
When either Timer1 or Timer3 is configured to
use
Asynchronous
T3CON<7:0> =
corresponding TMRxH:TMRxL registers may not
occur as expected.
For the purposes of this issue, instructions that
directly affect the contents of the Timer registers
are considered to be writes. This includes CLRF,
SETF and MOVF instructions.
received message is in the Message Assembly
Buffer (MAB).
(RXBxCON<RXFUL> set to '0') when a Start-
of-Frame (SOF) is recognized on the CAN bus
or on the instruction cycle prior to the SOF for
the TXBxSIDH corruption event to occur. The
timing of this event is crucial.
{
}
Temp_RXREG = RXBx; // Read receive buffer
If (MyFlag)
{
}
the
If (TXREQ == 1)// Is a transmission pending?
{
}
TXREQ = 1;
MyFlag = 0;
external
TXREQ = 0; // Clear transmit request
If (TXABT == 1)// Store transmission aborted status value
0xxx x111),
mode
MyFlag = 1;
clock
// Has an overflow occurred?
// Was previous transmission aborted?
// Set transmit request
// Reset stored transmission aborted status
(T1CON<7:0>
source
writes
in
to
8-Bit
the
or
EXAMPLE 2:
CLRF
MOVLW
MOVWF
Work around
Ensure that a receive buffer overflow condition
does not occur, and/or ensure that a transmit
request is not pending, if a received buffer
overflow condition does exist.
The pseudo code segment in Example 1 on the
following page is an example of how to disable a
pending transmission. This code is for illustration
purposes only.
Date Codes that pertain to this issue:
All engineering and production devices
Work around
Insert a delay of one instruction cycle between
writes to TMRxH and TMRxL. This delay can be a
NOP, or any instruction that does not access the
Timer registers (Example 2).
Date Codes that pertain to this issue:
All engineering and production devices.
TMR1H
T1Offset
TMR1L
; 1 Tcy delay
© 2007 Microchip Technology Inc.