PIC18LF4455T-I/PT Microchip Technology, PIC18LF4455T-I/PT Datasheet - Page 38
![IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,44PIN,PLASTIC](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC18LF4455T-I/PT
Manufacturer Part Number
PIC18LF4455T-I/PT
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,44PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PCM18XR1.pdf
(438 pages)
3.PIC18F2221-ISO.pdf
(46 pages)
4.PIC18F2455-ISO.pdf
(14 pages)
5.PIC18F2455-ISO.pdf
(8 pages)
6.PIC18F2455-ISO.pdf
(26 pages)
Specifications of PIC18LF4455T-I/PT
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
24KB (12K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SPI, I2C, EAUSART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
35
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163025
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF4455T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PCM18XR1 PDF datasheet #2
- PIC18F2221-ISO PDF datasheet #3
- PIC18F2455-ISO PDF datasheet #4
- PIC18F2455-ISO PDF datasheet #5
- PIC18F2455-ISO PDF datasheet #6
- Current page: 38 of 438
- Download datasheet (7Mb)
PIC18F2455/2550/4455/4550
3.1.3
The length of the transition between clock sources is
the sum of two cycles of the old clock source and three
to four cycles of the new clock source. This formula
assumes that the new clock source is stable.
Three bits indicate the current clock source and its
status. They are:
• OSTS (OSCCON<3>)
• IOFS (OSCCON<2>)
• T1RUN (T1CON<6>)
In general, only one of these bits will be set while in a
given power-managed mode. When the OSTS bit is
set, the primary clock is providing the device clock.
When the IOFS bit is set, the INTOSC output is provid-
ing a stable, 8 MHz clock source to a divider that
actually drives the device clock. When the T1RUN bit is
set, the Timer1 oscillator is providing the clock. If none
of these bits are set, then either the INTRC clock
source is clocking the device, or the INTOSC source is
not yet stable.
If the internal oscillator block is configured as the
primary clock source by the FOSC3:FOSC0 Con-
figuration bits, then both the OSTS and IOFS bits may
be set when in PRI_RUN or PRI_IDLE modes. This
indicates that the primary clock (INTOSC output) is
EXAMPLE 3-1:
3.2
In the Run modes, clocks to both the core and
peripherals are active. The difference between these
modes is the clock source.
3.2.1
The PRI_RUN mode is the normal, full-power execu-
tion mode of the microcontroller. This is also the default
mode upon a device Reset unless Two-Speed Start-up
is enabled (see Section 25.3 “Two-Speed Start-up”
for details). In this mode, the OSTS bit is set. The IOFS
bit may be set if the internal oscillator block is the
primary clock source (see Section 2.4.1 “Oscillator
Control Register”).
DS39632E-page 36
SLEEP
NOP
SLEEP
Run Modes
;Wait at least 1 Tcy before executing another sleep instruction
CLOCK TRANSITIONS AND
STATUS INDICATORS
PRI_RUN MODE
EXECUTING BACK TO BACK SLEEP INSTRUCTIONS
generating a stable 8 MHz output. Entering another
power-managed RC mode at the same frequency
would clear the OSTS bit.
3.1.4
The power-managed mode that is invoked with the
SLEEP instruction is determined by the setting of the
IDLEN bit at the time the instruction is executed. If
another SLEEP instruction is executed, the device will
enter the power-managed mode specified by IDLEN at
that time. If IDLEN has changed, the device will enter
the new power-managed mode specified by the new
setting.
Upon resuming normal operation after waking from
Sleep or Idle, the internal state machines require at
least one T
can be executed. If two back to back SLEEP instruc-
tions will be executed, the process shown in
Example 3-1 should be used.
3.2.2
The SEC_RUN mode is the compatible mode to the
“clock switching” feature offered in other PIC18
devices. In this mode, the CPU and peripherals are
clocked from the Timer1 oscillator. This gives users the
option of lower power consumption while still using a
high-accuracy clock source.
Note 1: Caution should be used when modifying a
2: Executing a SLEEP instruction does not
CY
MULTIPLE SLEEP COMMANDS
SEC_RUN MODE
single IRCF bit. If V
possible to select a higher clock speed
than is supported by the low V
Improper device operation may result if
the V
necessarily place the device into Sleep
mode. It acts as the trigger to place the
controller into either the Sleep mode, or
one of the Idle modes, depending on the
setting of the IDLEN bit.
delay before another SLEEP instruction
DD
/F
OSC
© 2009 Microchip Technology Inc.
specifications are violated.
DD
is less than 3V, it is
DD
.
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