PIC24FJ96GA008-I/PT Microchip Technology, PIC24FJ96GA008-I/PT Datasheet - Page 10
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PIC24FJ96GA008-I/PT
Manufacturer Part Number
PIC24FJ96GA008-I/PT
Description
IC,MICROCONTROLLER,16-BIT,PIC CPU,CMOS,TQFP,80PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheets
1.PIC24FJ16GA002-ISS.pdf
(52 pages)
2.PIC24FJ64GA006-IPT.pdf
(240 pages)
3.PIC24FJ64GA006-IPT.pdf
(22 pages)
Specifications of PIC24FJ96GA008-I/PT
Rohs Compliant
YES
Core Processor
PIC
Core Size
16-Bit
Speed
16MHz
Connectivity
I²C, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
96KB (32K x 24)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TFQFP
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
69
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011, DV164033, AC164127, MA240011
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1004 - PIC24 BREAKOUT BOARDDM240011 - KIT STARTER MPLAB FOR PIC24F MCUDV164033 - KIT START EXPLORER 16 MPLAB ICD2MA160011 - DAUGHTER BOARD PICDEM LCD 16F91XDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164328 - MODULE SKT FOR 80TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24FJ96GA008-I/PT
Manufacturer:
Maxim
Quantity:
164
Company:
Part Number:
PIC24FJ96GA008-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC24FJ96GA008-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC24FJ128GA010 FAMILY
25. Module: UART (Auto-Baud)
26. Module: Interrupts (Traps)
27. Module: Output Compare
DS80471A-page 10
With the auto-baud feature selected, the Sync
Break character (0x55) may be loaded into the
FIFO as data.
Work around
To prevent the Sync Break character from being
loaded into the FIFO, load the UxBRG register with
either 0x0000 or 0xFFFF prior to enabling the
auto-baud feature (ABAUD = 1).
Affected Silicon Revisions
The device may not exit Doze mode if certain trap
conditions occur. Address error, stack error and
math error traps are affected. Oscillator failure and
all interrupt sources are not affected and can
cause the device to correctly exit Doze mode.
Work around
None.
Affected Silicon Revisions
The output compare module may output a single
glitch for one T
(OCM<2:0> = 000). This issue occurs when the
output state of the associated Data Latch register
(LATx) is in the opposite state of the Output Com-
pare mode when the peripheral is enabled. It can
also occur when switching between two Output
Compare modes with opposite output states.
Work around
If the output glitch must be avoided, verify that the
associated data latch value of the OCx pin matches
the initial state of the desired Output Compare
mode. For example, if Output Compare 5 is
configured for mode, OCM<2:0> = 001, ensure that
the LATD<4> bit is clear prior to writing the OCM
bits. The port latch output value will match the initial
output state of the OC5 pin and avoid the glitch
when the peripheral is enabled.
Affected Silicon Revisions
A2
A2
A2
X
X
X
A3
A3
A3
X
X
X
A4
A4
A4
X
X
X
CY
after the module is enabled
C1
C1
C1
C2
C2
C2
28. Module: A/D (INT0 Trigger)
29. Module: SPI (Framed Modes)
With the External Interrupt 0 (INT0) selected to start
an A/D conversion (SSRC<2:0> = 001), the device
may not wake-up from Sleep or Idle mode if more
than one conversion is selected per interrupt
(SMPI<3:0> <> 0000). Interrupts are generated
correctly if the device is not in a Sleep or Idle mode.
Work around
Configure the A/D to generate an interrupt after
every
another wake-up source, such as the WDT or
another interrupt source, to exit the Sleep or Idle
mode. Alternatively, perform A/D conversions in
Run mode.
Affected Silicon Revisions
A frame synchronization pulse may not be output
in SPI Master mode if the pulse is selected to
coincide with the first bit clock (SPIFE = 1). SCKx
and SDOx waveforms are not affected.
Work around
Select the frame synchronization pulses to
precede the first bit clock (SPIFE = 0). The frame
pulses will output correctly as described in the
product data sheet.
Affected Silicon Revisions
A2
A2
X
X
A3
A3
conversion
X
X
A4
A4
X
X
© 2009 Microchip Technology Inc.
C1
C1
(SMPI<3:0> = 0000).
C2
C2
Use