S29AL008D70TFI020 Spansion Inc., S29AL008D70TFI020 Datasheet
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S29AL008D70TFI020
Specifications of S29AL008D70TFI020
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S29AL008D70TFI020 Summary of contents
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This document has not been approved. Sharing this document with non-Spansion employees violates QS9000/TS16949 requirements. S29AL008D 8 Megabit ( 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory Data Sheet Distinctive Characteristics Architectural Advantage Single power ...
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Notice On Data Sheet Designations Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, in- cluding development, qualification, initial production, and full production. In ...
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General Description The S29AL008D Mbit, 3.0 volt-only Flash memory organized as 1,048,576 bytes or 524,288 words. The device is offered in 48-ball FBGA, 44-pin SO, and 48-pin TSOP packages. For more information, refer to publication number 21536. ...
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The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. ...
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Table Of Contents Product Selector Guide Block Diagram . . . . . . . . . . ...
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Product Selector Guide Family Part Number Full Voltage Range: V Speed Options Regulated Voltage Range: V Max access time ACC Max CE# access time Max OE# access time Note: ...
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Connection Diagrams A15 1 A14 2 A13 3 A12 4 A11 5 A10 WE# RESET RY/BY# 15 A18 16 A17 ...
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Connection Diagrams RY/BY# A18 A17 CE OE# DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 A6 A13 WE# A3 RY/BY Special Handling Instructions ...
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Pin Configuration A0–A18 DQ0–DQ14 DQ15/A-1 BYTE# CE# OE# WE# RESET# RY/BY Logic Symbol June 16, 2005 S29AL008D_00A3 addresses = 15 data inputs/outputs = DQ15 ...
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Ordering Information Standard Products Spansion standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. S29AL008D DEVICE NUMBER/DESCRIPTION S29AL008D 8 Megabit Flash ...
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Device Bus Operations This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is com- posed of ...
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The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode ...
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The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V ± 0.3 V. (Note that this is a more restricted voltage range than CE# and RESET# are held ...
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Table 2. S29AL008D Top Boot Block Sector Addresses Sector A18 A17 A16 A15 SA0 SA1 SA2 SA3 SA4 SA5 0 ...
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Table 3. S29AL008D Bottom Boot Block Sector Addresses Sector A18 A17 A16 A15 SA0 SA1 SA2 SA3 SA4 SA5 0 ...
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Table 4. S29AL008D Autoselect Codes (High Voltage Method) Description Mode CE# Manufacturer ID: Spansion L Device ID: Word L Am29LV800B Byte L (Top Boot Block) Device ID: Word L Am29LV800B (Bottom Boot Byte L Block) Sector Protection L Verification L ...
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Figure 1 shows the algorithm, and grams, for this feature. Notes: 1. All protected sectors unprotected. 2. All previously protected sectors are protected once again. Figure 1. Temporary Sector Unprotect Operation June 16, 2005 S29AL008D_00A3 ...
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START PLSCNT = 1 RESET Wait First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes Set up sector address Sector Protect: Write 60h to sector address with ...
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Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to for command definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might ...
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The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the mand, next. See also Requirements for Reading Array Data, on page 11 The ...
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The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies ...
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Increment Address Note: See Table 5, on page 25 for program command sequence. Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is ini- tiated by writing two unlock cycles, followed by ...
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Figure 4, on page 25 / Program Operations, on page 42 timing diagrams. Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a ...
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Sector Erase time-out immediately terminates the time-out period and suspends the erase operation. Addresses are don’t-cares when writing the Erase Suspend command. When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of ...
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Notes: 1. See Table 5, on page 25 for erase command sequence. 2. See DQ3: Sector Erase Timer, on page 30 Table 5. S29AL008D Command Definitions Command Sequence (Note 1) Read (Note 6) 1 Reset (Note 7) 1 Word Manufacturer ...
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Legend Don’t care Address of the memory location to be read Data read from location RA during read operation, and PA = Address of the memory location to be programmed. Addresses latch on the ...
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Write Operation Status The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. subsections describe the functions of these bits. DQ7, RY/BY#, and DQ6 each offer a method for determining ...
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No Notes Valid address for programming. During a sector 2. DQ7 should be rechecked even if DQ5 = 1 because RY/BY#: Ready/Busy# The RY/BY dedicated, open-drain output pin that indicates whether an Em- bedded Algorithm ...
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If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend ...
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Thus, both status bits are required for sector and mode information. Refer to Table 6, on page 32 Figure 6, on page 31 section “DQ2: Toggle Bit II” explains the algorithm. See also the I, on page 29 ...
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See also the Command Sequence, on page Note 1 Notes: 1. Read toggle bit twice to determine whether or not it 2. Recheck toggle bit because it may stop toggling as ...
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To ensure the command is accepted, the sys- tem software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last ...
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Absolute Maximum Ratings Storage Temperature Plastic Packages . . . . . . . . . . . . . . . . .–65°C to +150°C Ambient Temperature with Power Applied . . . . . . . . . ...
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DC Characteristics Parameter Description I Input Load Current Input Load Current LIT I Output Leakage Current LO V Active Read Current CC I CC1 (Notes Active Write Current CC I CC2 (Notes 2, 3, ...
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DC Characteristics (Continued) Zero Power Flash 500 1000 Note: Addresses are switching at 1 MHz Figure 9. I Current vs. Time (Showing Active and Automatic Sleep Currents) CC1 ...
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Test Conditions Device Under Note: Nodes are IN3064 or equivalent. Test Condition Output Load Output Load Capacitance, C (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels 36 ...
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Key to Switching Waveforms WAVEFORM Don’t Care, Any Change Permitted 3.0 V 1.5 V Input 0.0 V Figure 12. Input Waveforms and Measurement Levels June 16, 2005 S29AL008D_00A3 INPUTS Steady Changing ...
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AC Characteristics Parameter JEDEC Std t t Read Cycle Time AVAV Address to Output Delay AVQV ACC t t Chip Enable to Output Delay ELQV Output Enable to Output Delay GLQV ...
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AC Characteristics Parameter JEDEC Std Description RESET# Pin Low (During Embedded t READY Algorithms) to Read or Write (See RESET# Pin Low (NOT During Embedded t READY Algorithms) to Read or Write (See t RESET# Pulse Width RP t RESET# ...
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AC Characteristics Table 10. Word/Byte Configuration (BYTE#) Parameter JEDEC Std t t CE# to BYTE# Switching Low or High ELFL/ ELFH t BYTE# Switching Low to Output HIGH Z FLQZ t BYTE# Switching High to Output Active FHQV 40 D ...
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CE# OE# BYTE# BYTE# DQ0–DQ14 Switching from word to byte mode DQ15/A-1 BYTE# BYTE# Switching DQ0–DQ14 from byte to word mode DQ15/A-1 Figure 15. BYTE# Timings for Read Operations CE# WE# BYTE# Note: Refer to the Erase/Program Operations table for ...
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AC Characteristics Erase / Program Operations Parameter JEDEC Std t t Write Cycle Time AVAV Address Setup Time AVWL Address Hold Time WLAX Data Setup Time DVWH Data ...
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AC Characteristics Program Command Sequence (last two cycles Addresses 555h CE Data RY/BY VCS Notes program address program data Illustration shows device ...
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AC Characteristics Erase Command Sequence (last two cycles Addresses 2AAh CE Data 55h RY/BY Notes sector address (for Sector Erase Valid ...
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AC Characteristics t RC Addresses VA t ACC OE# t OEH WE# DQ7 DQ0–DQ6 t BUS RY/BY# Note Valid address. Illustration shows first status cycle after command sequence, last status read ...
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AC Characteristics Enter Erase Embedded Suspend Erasing Erase Erase Suspend WE# DQ6 DQ2 Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector. Parameter JEDEC ...
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AC Characteristics RESET# SA, A6, A1, A0 Sector Protect/Unprotect Data 60h 1 μs CE# WE# OE# * For sector protect For sector unprotect ...
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AC Characteristics Table 12. Alternate CE# Controlled Erase/Program Operations Parameter JEDEC Std t t Write Cycle Time AVAV Address Setup Time AVEL Address Hold Time ELAX Data Setup Time DVEH DS ...
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AC Characteristics 555 for program 2AA for erase Addresses WE# OE# CE Data t R RESET# RY/BY# Notes program address program data, DQ7# = complement of the data written ...
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Under worst case conditions of 90° The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed the pre-programming step ...
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Physical Dimensions TS 048—48-Pin Standard TSOP * For reference only. BSC is an ANSI standard for Basic Space Centering. June 16, 2005 S29AL008D_00A3 S29AL008D Dwg rev AA; 10/99 51 ...
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Physical Dimensions VBK 048 - 48 Ball Fine-Pitch Ball Grid Array (FBGA) 8. INDEX MARK PIN A1 CORNER 10 TOP VIEW A SEATING PLANE A1 SIDE VIEW PACKAGE VBK 048 JEDEC N/A 6. 8.15 ...
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Physical Dimensions SO 044—44-Pin Small Outline Package June 16, 2005 S29AL008D_00A3 S29AL008D Dwg rev AC; 10/99 53 ...
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Revision Summary Revision A (September 8, 2004) Initial release Revision A 1 (February 18, 2005) Global Updated Trademark Ordering Information Added Package type designator Valid Combinations Changed Package Type, Material, and Temperature Range designator Under Package Descriptions, change SSOP to ...
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Erase/Program Operation Table Added 55ns speed option. Alternate CE# Controlled Erase/Program Operation Table Added 55ns speed option. Erase and Programming Performance Changed Byte Programing Time values for Typical and Maximum. Revision A3 (June 16, 2005) Changed from Preliminary to full ...