DG406DJ-E3 Vishay, DG406DJ-E3 Datasheet - Page 10

• Manufacturer Part Number: DG406DJ-E3
• Description: IC MUX CMOS ANLG DUAL 8CH 28-DIP
• Manufacturer: Vishay
• Type: Analog Multiplexerr

Specifications of DG406DJ-E3

• On Resistance (max): 120 Ohms
• Propagation Delay Time: 350 ns
• On Time (max): 600 ns
• Off Time (max): 300 ns
• Supply Voltage (max): 25 V
• Supply Current: 0.05 mA
• Maximum Power Dissipation: 625 mW
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Package / Case: PDIP-28
• Mounting Style: Through Hole
• Number Of Switches: Single
• Package: 28PDIP
• Maximum On Resistance: 120@12V Ohm
• Maximum Propagation Delay Bus To Bus: 350@±15V ns
• Maximum High Level Output Current: 30 mA
• Multiplexer Architecture: 16:1
• Maximum Turn-off Time: 300@12V ns
• Maximum Turn-on Time: 600@12V ns
• Power Supply Type: Single|Dual
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

DG406, DG407
Vishay Siliconix
APPLICATIONS HINTS
Sampling speed is limited by two consecutive events: the
transition time of the multiplexer, and the settling time of the
sampled signal at the output.
t
depends on several parameters: R
source impedance, multiplexer and load capacitances,
charge injection of the multiplexer and accuracy desired.
The settling time for the multiplexer alone can be derived
from the model shown in figure 5. Assuming a low
impedance signal source like that presented by an op amp or
a buffer amplifier, the settling time of the RC network for a
given accuracy is equal to n:
The maximum sampling frequency of the multiplexer is:
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?70061.
www.vishay.com
10
TRANS
f
s
=
Figure 5. Simplified Model of One Multiplexer Channel
N(t
% ACCURACY
where N = number of channels to scan
t
is given on the data sheet. Settling time at the load
SETTLING
SETTLING
0.0017
0.012
0.25
Figure 6. Measuring low-level analog signals is more accurate when using a differential multiplexing technique
1
R
S
+ t
= n = n x R
= 0
TRANS
Sensor 1
Sensor 8
To
To
R
)
DS(on)
DS(on)
# BITS
12
15
8
DS(on)
x C
C
D(on)
D(on)
V
of the multiplexer,
OUT
Multiplexer
DG407
Analog
11
N
6
9
(1)
Amp
Inst
For the DG406 then, at room temp and for 12-bit accuracy,
using the maximum limits:
or
f
From the sampling theorem, to properly recover the original
signal, the sampling frequency should be more than twice
the maximum component frequency of the original signal.
This assumes perfect bandlimiting. In a real application
sampling at three to four times the filter cutoff frequency is a
good practice.
Therefore from equation 2 above:
From this we can see that the DG406 can be used to sample
16 different signals whose maximum component frequency
can be as high as 173 kHz. If for example, two channels are
used to double sample the same incoming signal then its
cutoff frequency can be doubled.
The block diagram shown in Figure 6 illustrates a typical data
acquisition front end suitable for low-level analog signals.
Differential multiplexing of small signals is preferred since
this method helps to reject any common mode noise. This is
especially important when the sensors are located at a
distance and it may eliminate the need for individual
amplifiers. A low R
DG407 helps to reduce measurement errors. The low power
dissipation of the DG407 minimizes on-chip thermal
gradients which can cause errors due to temperature
mismatch along the parasitic thermocouple paths. Please
refer to Application Note AN203 for additional information.
f
s
f
s
c
= 694 kHz
Controller
=
=
16 (9 x 100 Ω x 10
1
4
x f
s
S/H
= 173 kHz
DS(on)
Converter
12-Bit
1
-12
A/D
, low leakage multiplexer like the
F) + 300 x 10
S11-0179-Rev. J, 07-Feb-11
Document Number: 70061
-12
s
(2)
(3)
(4)