LSM2-T/10-D12N-C Murata Power Solutions Inc, LSM2-T/10-D12N-C Datasheet - Page 15

• Manufacturer Part Number: LSM2-T/10-D12N-C
• Description: DC/DC Converter
• Manufacturer: Murata Power Solutions Inc

Specifications of LSM2-T/10-D12N-C

• Dc / Dc Converter O/p Type: Variable
• No. Of Outputs: 1
• Input Voltage: 8.3V To 14V
• Power Rating: 50W
• Output Voltage: 5V
• Output Current: 10A
• Approval Bodies: UL, CSA
• Supply Voltage: 12V
• Dc / Dc Converter Case Style: SMD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Guidelines for Sequence/Track Applications
[1] Leave the converter’s On/Off Enable control (if installed) in the On setting.
[2] Allow the converter to stabilize (typically less than 20 mS after +V
[3] If you do not use the Sequence/Track pin, leave it open or tied to +V
[4] Observe the Output slew rate relative to the Sequence input. A rough
[5] Be aware of the input characteristics of the Sequence pin. The high input
[6] Allow the converter to eventually achieve its full-rated setpoint output
[7] The Sequence is a sensitive input into the feedback control loop of the
Normally, you should just leave the On/Off pin open.
on) before raising the Sequence input. Also, if you wish to have a ramped
power down, leave +V
shut off power.
guide is 2 Volts per millisecond maximum slew rate. If you exceed this
slew rate on the Sequence pin, the converter will simply ramp up at
it’s maximum output slew rate (and will not necessarily track the faster
Sequence input). The reason to carefully consider the slew rate limitation
is in case you want two different POL’s to precisely track each other.
impedance affects the time constant of any small external ramp capacitor.
And the bias current will slowly charge up any external caps over time
if they are not grounded. The internal pull-up resistor to +V
400k: to 1M:.
Notice in the simplifi ed Sequence/Track equivalent circuit (Figure 17) that
a blocking diode effectively disconnects this circuit when the Sequence/
Track pin is pulled up to +V
voltage. Do not remain in ramp up/down mode indefi nitely. The converter
is characterized and meets all its specifi cations only at the setpoint volt-
age (plus or minus any trim voltage). During the ramp-up phase, the con-
verter is not considered fully in regulation. This may affect performance
with excessive high current loads at turn-on.
converter. Avoid noise and long leads on this input. Keep all wiring very
short. Use shielding if necessary. Consider adding a small parallel ceramic
capacitor across the Sequence/Track input (see Figure 16) to block any
external high frequency noise.
Figure 17. Sequence/Track Simplifi ed Equivalent Schematic
IN
powered all during the down ramp. Do not simply
IN
or left open.
IN
www.murata-ps.com
is typically
IN
power
IN
.
[8] If one converter is slaving to another master converter, there will be a very
[9] You may connect two or more Sequence inputs in parallel from two con-
[10] Any external capacitance added to the converter’s output may affect ramp
Power Good Output
The Power Good Output consists of an unterminated BSS138 small signal
fi eld effect transistor and a dual window comparator input circuit driving the
gate of the FET. Power Good is TRUE (open drain, high impedance state) if the
converter’s power output voltage is within about ±10% of the setpoint. Thus,
the PG TRUE condition indicates that the converter is approximately within
regulation. Since an overcurrent condition occurs at about 2% output voltage
reduction, the Power Good does not directly measure an output overcurrent
condition at rated maximum output current. However, gross overcurrent or an
output short circuit will set Power Good to FALSE (+0.2V saturation, low imped-
ance condition).
Common connection), the Power Good output is unterminated so that the user
may adapt the output to a variety of logic families. The PG pin may therefore
be used with logic voltages which are not necessarily the same as the input
or output power voltages. Install an external pullup resistor to the logic supply
voltage which is compatible with your logic system. When the Power Good is
out of limit, the FET is at saturation, approximately +0.2V output. Keep this
LOW (FALSE) pulldown current to less than 10mA.
Ignore Power Good while in transition.
Using a simple connection to external logic (and returned to the converter’s
Please note that Power Good is briefl y false during Sequence ramp-up.
short phase lag between the two converters. This can usually be ignored.
verters. Be aware of the increasing pull-up bias current and reduced input
impedance.
up/down times and ramp tracking accuracy.
Selectable-Output POL DC/DC Converters
Figure 18. Equivalent Power Good Circuit
25 Jun 2010
Single Output, Non-Isolated
MDC_LSM2
LSM2 Series
email: [e-mail]
Series.B09Δ
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