SMDA12C-5.TBT Semtech, SMDA12C-5.TBT Datasheet - Page 5
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SMDA12C-5.TBT
Manufacturer Part Number
SMDA12C-5.TBT
Description
TVS DIODE ARRAY, 300W, 12V, SOIC
Manufacturer
Semtech
Datasheet
1.SMDA12C-5.TBT.pdf
(7 pages)
Specifications of SMDA12C-5.TBT
Reverse Stand-off Voltage Vrwm
5V
Breakdown Voltage Range
16.7V
Clamping Voltage Vc Max
19V
Diode Configuration
Bidirectional
Peak Pulse Current Ippm
12A
Diode Case Style
SOIC
No. Of Pins
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SMDA12C-5.TBT
Manufacturer:
SEMTECH
Quantity:
9 073
Device Connection for Protection of Five Data Lines
The SMDAxxC-5 is designed to protect up to 5 data or
I/O lines. They are bidirectional devices and may be
used on lines where the signal polarities are above and
below ground.
The SMDAxxC-5 TVS arrays employ a monolithic struc-
ture. Therefore, the working voltage (V
down voltage (V
tial voltage between any two data line pins. For ex-
ample, the SMDA24C-5 is designed for a maximum
voltage excursion of ±12V between any two data lines.
The device is connected as follows:
Circuit Board Layout Recommendations for Suppres-
sion of ESD.
Good circuit board layout is critical for the suppression
of ESD induced transients. The following guidelines are
recommended:
Matte Tin Lead Finish
Matte tin has become the industry standard lead-free
replacement for SnPb lead finishes. A matte tin finish
is composed of 100% tin solder with large grains.
Since the solder volume on the leads is small com-
pared to the solder paste volume that is placed on the
land pattern of the PCB, the reflow profile will be
determined by the requirements of the solder paste.
Therefore, these devices are compatible with both
PROTECTION PRODUCTS
PROTECTION PRODUCTS
Applications Information
2004 Semtech Corp.
Pins 1, 2, 3, 4, and 5 are connected to the lines
that are to be protected. Pin 8 is connected to
ground. The ground connections should be made
directly to the ground plane for best results. The
path length is kept as short as possible to reduce
the effects of parasitic inductance in the board
traces. Pins 6 and 7 are not connected.
Place the TVS near the input terminals or connec-
tors to restrict transient coupling.
Minimize the path length between the TVS and the
protected line.
Minimize all conductive loops including power and
ground loops.
The ESD transient return path to ground should be
kept as short as possible.
Never run critical signals near board edges.
Use ground planes whenever possible.
BR
) specifications apply to the differen-
RWM
) and break-
5
SMDA05C-5 THRU SMDA24C-5
lead-free and SnPb assembly techniques. In addition,
unlike other lead-free compositions, matte tin does not
have any added alloys that can cause degradation of
the solder joint.
DATA IN
DATA IN
Connection Diagram
Circuit Diagram
8
1
7
2
6
3
5
4
www.semtech.com
DATA OUT
DATA OUT