AD9255-80EBZ Analog Devices Inc, AD9255-80EBZ Datasheet - Page 35

• Manufacturer Part Number: AD9255-80EBZ
• Description: A/D Converter Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9255-80EBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: ADC
• Kit Application Type: Data Converter
• Silicon Core Number: AD9255
• Kit Contents: Board
• Number Of Adc's: 1
• Number Of Bits: 14
• Sampling Rate (per Second): 80M
• Data Interface: Serial, SPI™
• Inputs Per Adc: 1 Differential
• Input Range: 1 ~ 2 Vpp
• Power (typ) @ Conditions: 239mW @ 80MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9255
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CONFIGURATION WITHOUT THE SPI
In applications that do not interface to the SPI control registers,
the SDIO/DCS pin and the SCLK/DFS pin serve as standalone
CMOS-compatible control pins. When the device is powered
up, it is assumed that the user intends to use the pins as static
control lines for the duty cycle stabilizer and output data format
feature control. In this mode, connect the CSB chip select to
AVDD, which disables the serial port interface.
The OEB pin, the DITHER pin, the LVDS pin, the LVDS_RS
pin, and the PDWN pin are active control lines in both external
pin mode and SPI mode. The input from these pins or the SPI
register setting (the logical OR of the SPI bit and the pin function)
is used to determine the mode of operation for the part.
Table 15. Mode Selection
Pin
SDIO/DCS
SCLK/DFS
OEB
PDWN
LVDS
LVDS_RS
DITHER
SCLK
SDIO
CSB
DON’T CARE
DON’T CARE
t
S
External
Voltage
SVDD (default)
AGND
SVDD
AGND (default)
DRVDD
AGND (default)
AVDD
AGND (default)
AGND (default)
AVDD
AGND (default)
AVDD
AGND (default)
AVDD
R/W
t
DS
W1
W0
t
DH
Configuration
Duty cycle stabilizer enabled
Duty cycle stabilizer disabled
Twos complement enabled
Offset binary enabled
Outputs in high impedance
Outputs enabled
Chip in power-down or
standby mode
Normal operation
CMOS output mode
LVDS output mode
ANSI LVDS output levels
Reduced swing LVDS
output levels
Dither disabled
Dither enabled
A12
t
HIGH
A11
t
Figure 84. Serial Port Interface Timing Diagram
LOW
A10
A9
Rev. A | Page 35 of 44
t
CLK
A8
A7
SPI ACCESSIBLE FEATURES
Table 16 provides a brief description of the general features that
are accessible via the SPI. These features are described in detail
in AN-877 Application Note, Interfacing to High Speed ADCs via
SPI. The AD9255 part-specific features are described in detail
following Table 17, the external memory map register table.
Table 16. Features Accessible Using the SPI
Feature Name
Mode
Clock
Offset
Test I/O
Output Mode
Output Phase
Output Delay
VREF
D5
D4
Description
Allows the user to set either power-down mode
or standby mode
Allows the user to access the DCS, set the
clock divider, set the clock divider phase, and
enable the SYNC input
Allows the user to digitally adjust the
converter offset
Allows the user to set test modes to have
known data on output bits
Allows the user to set the output mode
Allows the user to set the output clock polarity
Allows the user to vary the DCO delay
Allows the user to set the reference voltage
D3
D2
D1
D0
t
H
DON’T CARE
AD9255
DON’T CARE