IPR-RLDRAMII Altera, IPR-RLDRAMII Datasheet - Page 40

• Manufacturer Part Number: IPR-RLDRAMII
• Description: IP CORE Renewal Of IP-RLDRAMII
• Manufacturer: Altera
• Series: Memory Controllers - SDRAMr
• Type: MegaCorer

Specifications of IPR-RLDRAMII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Tool Function: Intellectual Property (IP) Core
• Supported Devices: HardCopy, Stratix
• Function: RLDRAM II Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Parameters
2–30
RLDRAM II Controller MegaCore Function User Guide
Note to
(1)
Enable external
impedance matching
Enable memory
device DLL
Number of address
and command busses
from FPGA to
memory for multiple
devices
Generate DM pins
Use dedicated PLL
outputs
Number of clock pairs
from FPGA to
memory
Table 2–8. Memory Initialization Options
Table 2–9. Memory Interface Parameters
The default signal is <signal>_0. When you specify additional address and command busses, both <signal>_0 and
<signal>_1 are present.
Parameter
Parameter
Table
2–9:
On or off
On or off
1 or 2
On or off
On or off
1 to 8
Range
Range
Table 2–9
shows the memory interface parameters.
Refer to your RLDRAM II data sheet.
Refer to your RLDRAM II data sheet.
–
–
–
–
MegaCore Version 9.1
Units
Depends on the number of devices. If you connect only
one device there can be only one address and command
bus.
Adds DM pins and logic to the design.
Turn on to use dedicated PLL outputs to generate the
clocks, which is recommended for HardCopy II devices.
When turned off
outputs.
The number of RLDRAM II clock output pairs generated in
the datapath. When you turn on Use dedicated clock
outputs, only values of 1 to 3 are valid.
(1)
altddio
Description
Description
outputs generate the clock
Altera Corporation
November 2009