KBR38A-PS2 Noritake Company Inc, KBR38A-PS2 Datasheet
![no-image](/images/no-image-200.jpg)
KBR38A-PS2
Manufacturer Part Number
KBR38A-PS2
Description
CABLE, IR RECEIVER
Manufacturer
Noritake Company Inc
Datasheet
1.KBR38A-1.pdf
(2 pages)
Specifications of KBR38A-PS2
Supply Voltage Range
4.75V To 5.25V
Carrier Frequency
38kHz
External Depth
9mm
External Length / Height
24mm
External Width
18mm
Operating Temperature Range
-40°C To +85°C
Opto Case Style
SIP
Supply
RoHS Compliant
IR Receiver Module
Electrical Parameter
Power Supply Voltage
Power Supply Current
Logic Input (not /RESET)
Logic Output
The /RESET input halts the CPU below 1/3 VDD and initializes above 2/3 VDD.
Environmental Parameter
Operating Temperature
Storage Temperature
Operating Humidity
OUTPUT MODES - Press CTRL then ALT then SHIFT then Key
Asynchronous serial 9600 baud – idle high – CMOS
Asynchronous serial 19200 baud – idle high – CMOS
Asynchronous serial 38400 baud – idle high – CMOS
Asynchronous serial 9600 baud – idle low – pseudo RS232
Asynchronous serial 19200 baud – idle low – pseudo RS232
Asynchronous serial 38400 baud – idle low – pseudo RS232
SPI synchronous slave clk input with data clocked on rising edge
SPI synchronous slave clk input with data clocked on falling edge
I2C with address 71H
Asynchronous serial 9600 baud – differential – RS485
Asynchronous serial 19200 baud – differential – RS485
Asynchronous serial 38400 baud – differential – RS485
SPI synchronous master clk output with data clocked on rising edge
SPI synchronous master clk output with data clocked on falling edge
3 Port Toggle – After power ON or /Reset ports are set to low output
Enable host busy handshaking or set /SS in SPI master
Disable host busy handshaking or set /STRB in SPI master (default)
1
DECODE OPTIONS - Press CTRL then ALT then SHIFT then Key
No decoding – outputs Raw RC5 command (00h – 38h)
No decoding – outputs Raw RC5 system (00h – 1Fh)
KBC56A keyboard ASCII decoding (default)
KBC56A offset RAW code SHIFT=+40h, ALT=+80h, CTRL=+C0h
CTRL, ALT and SHIFT are pressed before a single alternate character. CTRL then ALT
or CTRL then SHIFT enable ALT or SHIFT Lock which is cancelled using CTRL. When
lock is on, ALT or SHIFT can be used to input a related alternate character. A 16 byte
buffer allows the host system to poll the receiver every 2 seconds or to use the IRQ
generated by a key press when using I2C or hardware controlled asynchronous modes.
When the buffer is empty the data read is FFH in slave SPI or I2C modes and this can be
modified using SIN after the first byte in slave SPI mode. Data bytes are 8 bits with
asynchronous data adding 1 stop bit and no parity bit.
In Master SPI mode the /SS is low during data out
and /STRB is toggled low for 1us after data is
clocked out. The KBR38A-2 slave I2C interface
comprises a start condition, fixed address 71H, 8
bit data and stop condition.
Please see the KBR38A application notes on
page 2 for timing and circuit ideas.
*The RS232 interface operates between 0V and 5V. Do not connect pins 2, 4 and 6 to RS232 signals which exceed these values.
KBC56A, KBR38A and website content at
default mode for KBC38A-1.
18.0
NORITAKE ITRON IR CONTROLLERS
6.0
Pin pitch 2.54mm, dia 0.8mm
1
18.0
LED
Symbol
V
I
V
V
2
DD (typ)
DD
IL /
OL
default mode for KBC38A-2.
9.0
Max
V
/ V
IH
OH
www.KBC56A.com
SPI Master/Slave / I2C <1MHz clock
Async CMOS / RS232 / RS485
9600, 19200 and 38400 baud.
Single 5V supply at 13mA
LED shows Caps Lock & key press
User setup stored in EEPROM
ASCII / Raw data output modes.
The KBC38A-1 has SPI, Async CMOS,
RS232, RS485 and Port toggle interfaces.
The KBC38A-2 has SPI, I2C and Port
toggle interfaces. Use the KBC56A
keyboard to set up the operating mode of
the KBR38A or send the equivalent RC5
Raw data codes.
Value
5.0VDC +/- 5%
13mA + LED 2mA
0.8VDC max / 2.0VDC min
0.5VDC max / 2.4VDC min
Value
-40 C to +85 C
-40 C to +85 C
20 to 85% RH @ 25 C non condensing
PIN
1
1
2
3
4
5
6
HostBsy /HostBsy
/RESET /RESET /RESET
Async
TOUT
VDD
/IRQ
0V
are copyright 2008 Noritake Co. Limited, Japan.
2
RS232*
IRQ
VDD
TXD
0V
KBRVer
KBRVer
1 & 2
1 & 2
1 & 2
1 & 2
1 & 2
1 & 2
1 & 2
1 & 2
1 & 2
1 & 2
1 & 2
1
1
1
1
1
1
2
1
1
1
Condition
G
V
V
I
OH
DD
DD
ND
RS485
=-2mA
=0V
=5VDC
=5VDC
VDD
IRQ
+A
0V
-B
www.KBC56A.com
Key
Key
C
D
G
H
M
N
O
Q
R
U
A
B
E
F
K
L
P
S
T
J
I
KBR38A-1 / KBR38A-2
SPI Slave SPI Master
/RESET
CLK IN
SOUT
VDD
SIN
0V
Key
ESC
TAB
INS
DEL
▲PUp
◄HME
►END
▼PDn
?
*
(
)
1
2
3
4
5
6
7
8
9
0
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
q
r
s
t
u
v
w
x
y
z
‘
,
.
Space 20
Ctrl
Alt
Shift
Enter
I
J
L
T
!
;
:
£
$
F
R
€
¥
&
<
>
%
+
-
=
~
#
A
B
C
D
E
G
H
K
N
O
P
Q
S
U
V
X
Y
Z
@
W
M
“
°
|
[
]
\
/
/SS-/STRB
Std
1B
03
06
7F
0B
08
09
0A
3F
2A
28
29
31
32
33
34
35
36
37
38
39
30
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
27
2C
2E
CLK OUT
0D
/RESET
See application page 2 for specific
DOUT
functionality when these keys are
Data Decode Table (Hex)
VDD
0V
Shift
3C
2D
3D
4C
4D
0D
0E
9C
9D
9B
3E
2B
7E
4A
4B
4E
4F
5A
3B
3A
5F
01
04
10
12
14
16
18
24
40
26
25
23
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
21
Doc:32365 v2 11 July 2008
TogON TogOFF
Key H
Key G
pressed.
Key
Lock
4C
4D
2C
0C
33
34
35
36
37
38
39
30
41
42
43
44
45
46
47
48
49
4A
4B
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
27
2E
20
1B
7F
0B
0A
03
06
08
09
31
32
3F
2A
28
29
/RESET
I
VDD
0V
ALT
Hex
Hex
Hex
Hex
Hex
Hex
Hex
Hex
Hex
Hex
Hex
Hex
Hex
Hex
Hex
Hex
Key Q
Key O
Key P
0F
1C
1D
1E
1F
E0
E1
E2
E3
E4
E5
E6
E7
F0
F1
F2
F3
F4
F5
F6
F7
B2
F8
02
05
11
22
07
00
5C
5D
2F
5B
13
15
17
19
Page 1
CTRL Raw
AA
AB
AC
AD
AE
AF
80
81
83
82
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
B0
B1
B2
B3
B4
B8
/RESET
VDD
SCL
/IRQ
SDA
I2C
0V
0A
0B
0C
0D
0E
0F
1A
1B
1C
1D
1F
2A
2B
2C
2D
2E
2F
00
01
03
02
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
Related parts for KBR38A-PS2
KBR38A-PS2 Summary of contents
Page 1
... In Master SPI mode the /SS is low during data out and /STRB is toggled low for 1us after data is clocked out. The KBR38A-2 slave I2C interface comprises a start condition, fixed address 71H, 8 bit data and stop condition. ...
Page 2
... Then the fixed address of 71h is sent with R/W set high. The KBR38A-2 then responds with an ACK/NACK bit. The host must then issue 8 further clocks to clock data out. The host must then send an ACK on the 9 a stop condition is sent ...