JN5148/001,518 NXP Semiconductors, JN5148/001,518 Datasheet - Page 21

• Manufacturer Part Number: JN5148/001,518
• Description: MCU 802.15.4 32BIT 2.4G 56-QFN
• Manufacturer: NXP Semiconductors
• Series: JN5148r

Specifications of JN5148/001,518

• Frequency: 2.4GHz
• Data Rate - Maximum: 667kbps
• Modulation Or Protocol: 802.15.4
• Applications: Home/Building Automation, Industrial Control
• Power - Output: 2.5dBm
• Sensitivity: -95dBm
• Voltage - Supply: 2 V ~ 3.6 V
• Current - Receiving: 17.5mA
• Current - Transmitting: 15mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB RAM, 128kB ROM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 56-VFQFN
• Core: RISC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6 Reset
A system reset initialises the device to a pre-defined state and forces the CPU to start program execution from the
reset vector. The reset process that the JN5148 goes through is as follows.
When power is applied, the 32kHz RC oscillator starts up and stabilises, which takes approximately 100μsec. At this
point, the 32MHz crystal oscillator is enabled and power is applied to the processor and peripheral logic. The logic
blocks are held in reset until the 32MHz crystal oscillator stabilises, typically this takes 0.75ms. Then the internal
reset is removed from the CPU and peripheral logic and the CPU starts to run code beginning at the reset vector,
consisting of initialisation code and the resident boot loader. [7] Section 22.3.1 provides detailed electrical data and
timing.
The JN5148 has five sources of reset:
6.1 Internal Power-on Reset
For the majority of applications the internal power-on reset is capable of generating the required reset signal. When
power is applied to the device, the power-on reset circuit monitors the rise of the VDD supply. When the VDD
reaches the specified threshold, the reset signal is generated and can be observed as a rising edge on the RESETN
pin. This signal is held internally until the power supply and oscillator stabilisation time has elapsed, when the internal
reset signal is then removed and the CPU is allowed to run.
When the supply drops below the power on reset ‘falling’ threshold, it will re-trigger the reset. Use of the external
reset circuit show in Figure 12 is suggested.
© NXP Laboratories UK 2010
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Internal Power-on Reset
External Reset
Software Reset
Watchdog timer
Brown-out detect
Note: When the device exits a reset condition, device operating
parameters (voltage, frequency, temperature, etc.) must be met to ensure
operation. If these conditions are not met, then the device must be held in
reset until the operating conditions are met. (See section 22.3)
Internal RESET
RESETN Pin
VDD
Figure 11: Internal Power-on Reset
JN-DS-JN5148-001 1v6
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