JN5148/001,515 NXP Semiconductors, JN5148/001,515 Datasheet - Page 44
JN5148/001,515
Manufacturer Part Number
JN5148/001,515
Description
MCU 802.15.4 32BIT 2.4G 56-QFN
Manufacturer
NXP Semiconductors
Series
JN5148r
Datasheet
1.JN5148-UG010.pdf
(99 pages)
Specifications of JN5148/001,515
Frequency
2.4GHz
Data Rate - Maximum
667kbps
Modulation Or Protocol
802.15.4
Applications
Home/Building Automation, Industrial Control
Power - Output
2.5dBm
Sensitivity
-95dBm
Voltage - Supply
2 V ~ 3.6 V
Current - Receiving
17.5mA
Current - Transmitting
15mA
Data Interface
PCB, Surface Mount
Memory Size
128kB RAM, 128kB ROM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
56-VFQFN
Core
RISC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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12 Pulse Counters
Two 16-bit counters are provided that can increment during all modes of operation (including sleep), based on pulses
received on 2 dedicated DIO inputs; DIO1 and DIO8. The pulses can be de-bounced using the 32kHz clock to guard
against false counting on slow or noisy edges. Increments occur from a configurable rising or falling edge on the
respective DIO input.
Each counter has an associated 16-bit reference that is loaded by the user. An interrupt (and wakeup event if
asleep) may be generated when a counter reaches its pre-configured reference value. The two counters may
optionally be cascaded together to provide a single 32-bit counter, linked to DIO1. The counters do not saturate at
65535, but naturally roll-over to 0. Additionally, the pulse counting continues when the reference value is reached
without software interaction so that pulses are not missed even if there is a long delay before an interrupt is serviced
or during the wakeup process.
The system can work with signals up to 100kHz, with no debounce, or from 5.3kHz to 1.7kHz with debounce. When
using debounce the 32kHz clock must be active, so for minimum sleep currents the debounce mode should not be
used.
44
JN-DS-JN5148-001 1v6
© NXP Laboratories UK 2010
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